■ ML53612 ■ ––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
4.2 CT Bus
The ML53612 provides access to all 4096 CT Bus time-slots. The upper 16 data lines run at 8 Mbps, while
the lower 16 data lines can be configured, in groups of four, to run at 8 Mbps, 4 Mbps, or 2 Mbps for com-
patibility with SCbus and MVIP-90 devices.
The chip uses an internal analog phase locked loop (PLL) as a rate multiplier to produce a 131.072 MHz
internal clock locked to a variety of reference frequencies. This high frequency internal clock provides
fine grained correction steps (7.6 nS) for the master and slave digital PLLs. The main CT Bus network ref-
erence signal can be configured to run at 8 kHz, 1.544 MHz, or 2048 MHz. The timing for the CT Bus can
be configured to be derived from the local clock and frame sync signals to allow multiple chips to be con-
nected to the CT Bus without overloading the reference clock line.
The ML53612 incorporates internal master digital PLL circuitry that is designed to meet the jitter attenu-
ation, holdover and Maximum Time Interval Error (MTIE) requirements of the AT&T 62411 Stratum 3, 4
and 4E. This enables the ML53612 to be well suited for developers of digital telephone network inter-
faces, where reliable clock synchronization is critical. Because the circuitry is internal, board designers do
not have to add expensive or custom circuitry to support these types of environments.
The ML53612 also includes an 8-channel stream-to-stream switch to connect one CT Bus data stream to
another at the same or different data rates. This type of connection makes it possible for CT Bus compat-
ible devices (such as SCbus and MVIP-90) to efficiently exchange data even though they operate at differ-
ent rates. This stream switch enables switching between any of the 32 CT Bus data streams operating at
2, 4, or 8 Mbps. Depending upon the data stream rates, the stream switch provides a minimum of 256 and
a maximum of 1024 unidirectional time-slot connections. Stream switches in other ML53612 devices,
within a system, may be used simultaneously to increase switching capability.
4.3 Test Access Port
The ML53612 supports IEEE 1-149.1 Boundary Scan. For Normal operation, the TRST_N pin should be
driven low.
4.4 Pin Continuity Test
For normal operation, the TEST pin is driven low. When the TEST pin is high, all pins except VDD, VSS,
NC, APLL_PC, APLL_VCO, TMS, TCK, TRST_N, TDI, TDO, TEST are sequentially "NAND’ed" with
ALE and output on TDO. This test allows each input pin to be toggled and a corresponding output to be
observed on the TDO pin to verify the proper connection of the ML53612 to a printed circuit board.
4.5 Analog PLL Test
For normal operation, the APLL_TEST pin is driven low.
4.6 Microprocessor Interface
Both Intel and Motorola microprocessor bus interfaces are supported. Drive I_N (M) low for Intel mode
and high for Motorola mode. Multiplexed addresses are latched on the falling edge of ALE (AS). If mul-
tiplexed address is not used, drive ALE (AS) high. Multiplexed address and data must be connected to
both A_ and D_ pins.
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Oki Semiconductor
OKI [ OKI ELECTRONIC COMPONETS ]
