NXP Semiconductors
PF4210
14-channel power management integrated circuit (PMIC) for audio/video applications
Symbol
Parameter
Min
Typ
Max
Unit
[1]
VIN3
Operating input voltage
V
1.8 V ≤ VGEN5NOM ≤ 2.5 V
2.6 V ≤ VGEN5NOM ≤ 3.3 V
2.8
—
—
4.5
4.5
VGEN5NOM
+ 0.250
VGEN5NOM
IGEN5
Nominal output voltage
Operating load current
—
Table 91
—
—
V
0.0
100
mA
VGEN5 active mode – DC
VGEN5TOL
Output voltage tolerance
%
VIN3MIN < VIN3 < 4.5 V
−3.0
—
3.0
0.0 mA < IGEN5 < 100 mA
VGEN5[3:0] = 0000 to 1111
VGEN5LOR
Load regulation
mV/mA
mV/mA
(VGEN5 at IGEN5 = 100 mA) − (VGEN5 at IGEN5
= 0.0 mA)
For any VIN3MIN < VIN3 < 4.5 mV
—
—
0.10
0.50
—
—
VGEN5LIR
Line regulation
(VGEN5 at VIN3 = 4.5 V) − (VGEN5 at VIN3MIN
)
For any 0.0 mA < IGEN5 < 100 mA
IGEN5LIM
IGEN5OCP
IGEN5Q
Current limit
mA
mA
µA
IGEN5 when VGEN5 is forced to
VGEN5NOM/2
122
120
—
167
—
200
200
—
Overcurrent protection threshold
IGEN5 required to cause the SCP function to
disable LDO when REGSCPEN = 1
Quiescent current
No load, change in IVIN and IVIN3
When VGEN5 enabled
13
VGEN5 AC and transient
[2]
PSRRVGEN5
PSRR
dB
IGEN5 = 75 mA, 20 Hz to 20 kHz
VGEN5[3:0] = 0000 to 1111, VIN3 = VIN3MIN
+ 100 mV
35
52
40
60
—
—
VGEN5[3:0] = 0000 to 1111, VIN3
VGEN5NOM + 1.0 V
=
NOISEVGEN5
Output noise density
VIN3 = VIN3MIN, IGEN5 = 75 mA
100 Hz to <1.0 kHz
dBV/√Hz
mV/µs
—
—
—
−114
−129
−135
−102
−123
−130
1.0 kHz to <10 kHz
10 kHz to 1.0 MHz
SLWRVGEN5
Turn on slew rate
10 % to 90 % of end value
VIN3MIN ≤ VIN3 ≤ 4.5 mV, IGEN5 = 0.0 mA
VGEN5[3:0] = 0000 to 0011
VGEN5[3:0] = 0100 to 0111
VGEN5[3:0] = 1000 to 1011
VGEN5[3:0] = 1100 to 1111
—
—
—
—
—
—
—
—
22.0
26.5
30.5
34.5
PF4210
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2018. All rights reserved.
Data sheet: technical data
Rev. 2.0 — 14 November 2018
97 / 137
NXP [ NXP ]
