NXP Semiconductors
PF4210
14-channel power management integrated circuit (PMIC) for audio/video applications
PF4210
V
IN
2.25 V (VTLO) - 4.5
LDO/SWITCH
INPUT
SENSE/
SELECTOR
LICELL
CHARGER
V
REF
VSNVS
COIN CELL
Z
1.8 V TO 3.3 V
2
I C INTERFACE
aaa-026500
Figure 31.ꢀVSNVS supply switch architecture
Table 106 provides a summary of the VSNVS operation at different input voltage VIN and
with or without coin cell connected to the system.
Table 106.ꢀVSNVS modes of operation
VSNVSVOLT[2:0]
110
VIN
Mode
> VTH1
< VTL1
> VTH0
< VTL0
VIN LDO 3.0 V
Coin cell switch
VIN LDO
110
000 to 101
000 to 101
Coin cell LDO
10.4.6.6.1 VSNVS control
The VSNVS output level is configured through the VSNVSVOLT[2:0] bits in VSNVSCTL
register as shown in Table 107.
Table 107.ꢀRegister VSNVSCTL - ADDR 0x6B
Name
Bit number
R/W
Default Description
0x80
Configures VSNVS output voltage [1]
VSNVSVOLT
2:0
R/W
• 000 = 1.0 V
• 001 = 1.1 V
• 010 = 1.2 V
• 011 = 1.3 V
• 100 = 1.5 V
• 101 = 1.8 V
• 110 = 3.0 V
• 111 = RSVD
UNUSED
7:3
—
0x00
unused
[1] Only valid when a valid input voltage is present.
10.4.6.6.2 VSNVS external components
Table 108.ꢀVSNVS external components
Capacitor
Value (µF)
VSNVS
0.47
PF4210
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2018. All rights reserved.
Data sheet: technical data
Rev. 2.0 — 14 November 2018
101 / 137
NXP [ NXP ]
