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MC34PF4210A0ES 参数 Datasheet PDF下载

MC34PF4210A0ES图片预览
型号: MC34PF4210A0ES
PDF下载: 下载PDF文件 查看货源
内容描述: [14-channel power management integrated circuit (PMIC) for audio/video applications]
分类和应用: 集成电源管理电路
文件页数/大小: 137 页 / 1328 K
品牌: NXP [ NXP ]
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NXP Semiconductors  
PF4210  
14-channel power management integrated circuit (PMIC) for audio/video applications  
Symbol  
Parameter  
Min  
Typ  
Max  
Unit  
VGEN6LOTR  
Transient load response  
VIN3 = VIN3MIN, 4.5 V  
%
3.0  
IGEN6 = 20 to 200 mA in 1.0 µs  
Peak of overshoot or undershoot of VGEN6  
with respect to final value. See Figure 30.  
VGEN6LITR  
Transient line response  
IGEN6 = 150 m  
mV  
VIN3INITIAL = 2.8 V to VIN3FINAL = 3.3 V for  
VGEN6[3:0] = 0000 to 0111  
5.0  
8.0  
VIN3INITIAL = VGEN6 + 0.3 V to VIN3FINAL  
= VGEN6 + 0.8 V for VGEN6[3:0] = 1000 to  
1111  
See Figure 30  
[1] When the LDO output voltage is set above 2.6 V the minimum allowed input voltage need to be at least the output voltage plus 0.25 V for proper  
regulation due to the dropout voltage generated through the internal LDO transistor.  
[2] The PSRR of the regulators is measured with the perturbing signal at the input of the regulator. The power management IC is supplied separately from  
the input of the regulator and does not contain the perturbed signal. During measurements, care must be taken not to operate in the dropout region of the  
regulator under test. VIN3MIN refers to the minimum allowed input voltage for a particular output voltage.  
10.4.6.6 VSNVS LDO/switch  
VSNVS powers the low-power SNVS/RTC domain on the processor. It derives its power  
from either VIN, or coin cell, and cannot be disabled. When powered by both, VIN takes  
precedence when above the appropriate comparator threshold. When powered by VIN,  
VSNVS is an LDO capable of supplying seven voltages: 3.0, 1.8, 1.5, 1.3, 1.2, 1.1, and  
1.0. The bits VSNVSVOLT[2:0] in register VSNVS_CONTROL determine the output  
voltage. When powered by coin cell, VSNVS is an LDO capable of supplying 1.8, 1.5,  
1.3, 1.2, 1.1, 1.0 as shown in Table 106.  
If the 3.0 V option is chosen with the coin cell, VSNVS tracks the coin cell voltage by  
means of a switch, whose maximum resistance is 100 Ω. In this case, the VSNVS  
voltage is simply the coin cell voltage minus the voltage drop across the switch, which  
is 40 mV at a rated maximum load current of 1.5 mA (consumer version) or 1.0 mA  
(industrial version).  
The default setting of the VSNVSVOLT[2:0] is 110, or 3.0 V, unless programmed  
otherwise in OTP. However, when the coin cell is applied for the very first time, VSNVS  
outputs 1.0 V. Only when VIN is applied, VSNVS transitions to its default, or programmed  
value if different. Upon subsequent removal of VIN, with the coin cell attached, VSNVS  
changes configuration from an LDO to a switch for the 110 setting, and remains as an  
LDO for the other settings, continuing to output the same voltage as when VIN is applied,  
provided certain conditions are met as described in Table 106.  
PF4210  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2018. All rights reserved.  
Data sheet: technical data  
Rev. 2.0 — 14 November 2018  
100 / 137  
 
 
 
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