NXP Semiconductors
PF4210
14-channel power management integrated circuit (PMIC) for audio/video applications
Number Name
Function Max rating
Type
Definition
30
VINREFDDR
Input
3.6 V
Analog
VREFDDR regulator input. Bypass with at least 1.0 µF
decoupling capacitor as close to the pin as possible.
31
32
VREFDDR
Output
3.6 V
—
Analog
GND
VREFDDR regulator output
SW3VSSSNS GND
Ground reference for the SW3 regulator. Connect to
GNDREF externally via the board ground plane.
33
34
SW3BFB [1]
SW3BIN [1]
Input
Input
3.6 V
4.8 V
Analog
Analog
Output voltage feedback for SW3B. Route this trace
separately from the high current path and terminate at the
output capacitance.
Input to SW3B regulator. Bypass with at least a 4.7 µF
ceramic capacitor and a 0.1 µF decoupling capacitor as
close to the pin as possible.
35
36
37
SW3BLX [1]
SW3ALX [1]
SW3AIN [1]
Output
Output
Input
4.8 V
4.8 V
4.8 V
Analog
Analog
Analog
Regulator 3B switch node connection
Regulator 3A switch node connection
Input to SW3A regulator. Bypass with at least a 4.7 µF
ceramic capacitor and a 0.1 µF decoupling capacitor as
close to the pin as possible.
38
SW3AFB [1]
Input
3.6 V
Analog
Output voltage feedback for SW3A. Route this trace
separately from the high current path and terminate at the
output capacitance.
39
40
41
42
VGEN5
VIN3
Output
Input
3.6 V
4.8 V
3.6 V
Analog
Analog
Analog
Analog
VGEN5 regulator output. Bypass with a 2.2 µF ceramic
output capacitor.
VGEN5, 6 input. Bypass with a 1.0 µF decoupling
capacitor as close to the pin as possible.
VGEN6
LICELL
Output
VGEN6 regulator output. Bypass with a 2.2 µF ceramic
output capacitor.
Input/Out 3.6 V
put
Coin cell supply input/output
43
44
VSNVS
SWBSTFB [1]
Output
Input
3.6 V
5.5 V
Analog
Analog
LDO or coin cell output to processor
Boost regulator feedback. Connect this pin to the output
rail close to the load. Keep this trace away from other
noisy traces and planes.
45
SWBSTIN [1]
Input
4.8 V
Analog
Analog
Input to SWBST regulator. Bypass with at least a 2.2 µF
ceramic capacitor and a 0.1 µF decoupling capacitor as
close to the pin as possible.
46
47
SWBSTLX [1]
VDDOTP
Output
Input
7.5 V
10 V [2]
SWBST switch node connection
Supply to program OTP fuses
Digital/
Analog
48
49
50
51
52
53
GNDREF
VCORE
VIN
GND
—
GND
Ground reference for the main band gap regulator
Analog core supply
Output
Input
3.6 V
4.8 V
1.5 V
1.5 V
Analog
Analog
Analog
Analog
Digital
Main chip supply
VCOREDIG
VCOREREF
SDA
Output
Output
Digital core supply
Main band gap reference
I2C data line (open drain)
Input/Out 3.6 V
put
PF4210
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© NXP B.V. 2018. All rights reserved.
Data sheet: technical data
Rev. 2.0 — 14 November 2018
7 / 137
NXP [ NXP ]
