NXP Semiconductors
PF4210
14-channel power management integrated circuit (PMIC) for audio/video applications
Number Name
Function Max rating
Type
Definition
8
SW1ALX [1]
SW1BLX [1]
SW1BIN [1]
Output
Output
Input
4.8 V
4.8 V
4.8 V
Analog
Analog
Analog
Regulator 1A switch node connection
Regulator 1B switch node connection
9
10
Input to SW1B regulator. Bypass with at least a 4.7 µF
ceramic capacitor and a 0.1 µF decoupling capacitor as
close to the pin as possible.
11
12
SW1CLX [1]
SW1CIN [1]
Output
Input
4.8 V
4.8 V
Analog
Analog
Regulator 1C switch node connection
Input to SW1C regulator. Bypass with at least a 4.7 µF
ceramic capacitor and a 0.1 µF decoupling capacitor as
close to the pin as possible.
13
SW1CFB [1]
Input
3.6 V
Analog
Output voltage feedback for SW1C. Route this trace
separately from the high current path and terminate at the
output capacitance.
14
15
SW1VSSSNS GND
—
—
GND
GND
Ground reference for regulators SW1ABC. It is connected
externally to GNDREF through a board ground plane.
GNDREF1
GND
Ground reference for regulators SW2 and SW4. It is
connected externally to GNDREF, via board ground
plane.
16
17
18
19
VGEN1
VIN1
Output
Input
2.5 V
3.6 V
2.5 V
3.6 V
Analog
Analog
Analog
Analog
VGEN1 regulator output. Bypass with a 2.2 µF ceramic
output capacitor.
VGEN1, 2 input supply. Bypass with a 1.0 µF decoupling
capacitor as close to the pin as possible.
VGEN2
SW4FB [1]
Output
Input
VGEN2 regulator output. Bypass with a 4.7 µF ceramic
output capacitor.
Output voltage feedback for SW4. Route this trace
separately from the high current path and terminate at the
output capacitance.
20
SW4IN [1]
Input
4.8 V
Analog
Input to SW4 regulator. Bypass with at least a 4.7 µF
ceramic capacitor and a 0.1 µF decoupling capacitor as
close to the pin as possible.
21
22
23
24
SW4LX [1]
SW2LX [1]
SW2IN [1]
SW2IN [1]
Output
Output
Input
4.8 V
4.8 V
4.8 V
4.8 V
Analog
Analog
Analog
Analog
Regulator 4 switch node connection
Regulator 2 switch node connection
Input to SW2 regulator. Connect pin 23 together with pin
24 and bypass with at least a 4.7 µF ceramic capacitor
and a 0.1 µF decoupling capacitor as close to these pins
as possible.
Input
25
SW2FB [1]
Input
3.6 V
Analog
Output voltage feedback for SW2. Route this trace
separately from the high current path and terminate at the
output capacitance.
26
27
28
29
VGEN3
VIN2
Output
Input
3.6 V
3.6 V
3.6 V
3.6 V
Analog
Analog
Analog
Analog
VGEN3 regulator output. Bypass with a 2.2 µF ceramic
output capacitor.
VGEN3, 4 input. Bypass with a 1.0 µF decoupling
capacitor as close to the pin as possible.
VGEN4
VHALF
Output
Input
VGEN4 regulator output. Bypass with a 4.7 µF ceramic
output capacitor.
Half supply reference for VREFDDR
PF4210
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2018. All rights reserved.
Data sheet: technical data
Rev. 2.0 — 14 November 2018
6 / 137
NXP [ NXP ]
