NXP Semiconductors
PF4210
14-channel power management integrated circuit (PMIC) for audio/video applications
7 Pinning information
7.1 Pinning
PF4210
1
2
42
41
40
39
38
37
36
35
34
33
32
31
30
29
INTB
SDWNB
LICELL
VGEN6
3
RESETBMCU
STANDBY
ICTEST
VIN3
4
VGEN5
5
SW3AFB
SW3AIN
SW3ALX
SW3BLX
SW3BIN
SW3BFB
SW3VSSSNS
VREFDDR
VINREFDDR
VHALF
6
SW1FB
7
SW1AIN
EP
8
SW1ALX
SW1BLX
SW1BIN
9
10
11
12
13
14
SW1CLX
SW1CIN
SW1CFB
SW1VSSSNS
aaa-026472
Transparent top view
Figure 3.ꢀPinout diagram
7.2 Pin definitions
Table 2.ꢀPin definitions
Number Name
Function Max rating
Type
Definition
1
2
INTB
Output
Output
3.6 V
3.6 V
Digital
Digital
Open drain interrupt signal to processor
SDWNB
Open drain signal to indicate an imminent system
shutdown
3
RESETBMCU Output
3.6 V
Digital
Open drain reset output to processor. Alternatively can be
used as a power output.
4
5
STANDBY
ICTEST
Input
Input
3.6 V
7.5 V
Digital
Standby input signal from processor
Digital/
Analog
Reserved pin. Connect to GND in application.
6
7
SW1FB [1]
SW1AIN [1]
Input
Input
3.6 V
4.8 V
Analog
Output voltage feedback for SW1A/B. Route this trace
separately from the high current path and terminate at the
output capacitance.
Analog
Input to SW1A regulator. Bypass with at least a 4.7 µF
ceramic capacitor and a 0.1 µF decoupling capacitor as
close to the pin as possible.
PF4210
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© NXP B.V. 2018. All rights reserved.
Data sheet: technical data
Rev. 2.0 — 14 November 2018
5 / 137
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