NXP Semiconductors
PF4210
14-channel power management integrated circuit (PMIC) for audio/video applications
Name
Bit number
R/W
Default Description
SW3AOFF
6
R
0x00
Sets the operating output voltage range for SW3A
(independent) or SW3A/B (single/dual phase) in sleep mode.
This bit inherits the value configured on bit SW3A[6] during
OTP or TBB configuration. See Table 63 for all possible
configurations.
UNUSED
7
—
0x00
unused
Table 68.ꢀRegister SW3AMODE - ADDR 0x3F
Name
Bit number
R/W
Default Description
SW3AMODE
3:0
R/W
0x08
Sets the SW3A (independent) or SW3A/B (single/dual phase)
switching operation mode. See Table 29 for all possible
configurations.
UNUSED
4
5
—
0x00
0x00
unused
SW3AOMODE
R/W
Set status of SW3A (independent) or SW3A/B (single/dual
phase) when in sleep mode.
• 0 = OFF
• 1 = PFM
UNUSED
7:6
—
0x00
unused
Table 69.ꢀRegister SW3ACONF - ADDR 0x40
Name
Bit number
R/W
Default Description
SW3AILIM
0
R/W
0x00
SW3A current limit level selection
• 0 = High-level current limit
• 1 = Low-level current limit
UNUSED
1
R/W
R/W
R/W
R/W
0x00
0x00
0x00
0x00
unused
SW3AFREQ
SW3APHASE
SW3ADVSSPEED
3:2
5:4
7:6
SW3A switching frequency selector. See Table 36.
SW3A phase clock selection. See Table 34.
SW3A DVS speed selection. See Table 33.
Table 70.ꢀRegister SW3BVOLT - ADDR 0x43
Name
Bit number
R/W
Default Description
SW3B
5:0
R/W
0x00
Sets the SW3B output voltage (independent) during normal
operation mode. See Table 63 for all possible configurations.
SW3B
6
7
R
–
0x00
Sets the operating output voltage range for SW3B
(independent). Set during OTP or TBB configuration only. See
Table 63 for all possible configurations.
UNUSED
0x00
unused
PF4210
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© NXP B.V. 2018. All rights reserved.
Data sheet: technical data
Rev. 2.0 — 14 November 2018
68 / 137
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