NXP Semiconductors
PF4210
14-channel power management integrated circuit (PMIC) for audio/video applications
VIN
SW3AIN
SW3AMODE
I
SENSE
C
INSW3A
CONTROLLER
SW3
SW3ALX
DRIVER
L
SW3A
SW3AFAULT
C
OSW3A
INTERNAL
COMPENSATION
I2C
2
Z2
I C
SW3AFB
SW3BIN
INTERFACE
Z1
EA
V
DAC
REF
VIN
SW3BMODE
I
SENSE
C
INSW3B
CONTROLLER
SW3BLX
EP
SW3B
DRIVER
L
SW3B
SW3BFAULT
C
OSW3B
INTERNAL
COMPENSATION
I2C
Z2
SW3BFB
Z1
EA
V
REF
DAC
aaa-026491
Figure 22.ꢀSW3A/B independent output block diagram
10.4.4.5.4 SW3A/B setup and control registers
SW3A/B output voltage is programmable from 0.400 V to 3.300 V; however, bit SW3x[6]
in register SW3xVOLT is read-only during normal operation. Its value is determined by
the default configuration, or may be changed by using the OTP registers. Therefore, once
SW3x[6] is set to 0, the output is limited to the lower output voltage range from 0.40 V
to 1.975 V with 25 mV increments, as determined by bits SW3x[5:0]. Likewise, once bit
SW3x[6] is set to 1, the output voltage is limited to the higher output voltage range from
0.800 V to 3.300 V with 50 mV increments, as determined by bits SW3x[5:0].
In order to optimize the performance of the regulator, it is recommended only voltage
from 2.00 V to 3.300 V be used in the high range and the lower range be used for voltage
from 0.400 V to 1.975 V.
The output voltage set point is independently programmed for normal, standby, and sleep
mode by setting the SW3x[5:0], SW3xSTBY[5:0], and SW3xOFF[5:0] bits respectively;
however, the initial state of the SW3x[6] bit is copied into the SW3xSTBY[6] and
SW3xOFF[6] bits. Therefore, the output voltage range remains the same on all three
operating modes. Table 63 shows the output voltage coding valid for SW3x.
Note: Voltage set points of 0.6 V and below are not supported.
PF4210
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© NXP B.V. 2018. All rights reserved.
Data sheet: technical data
Rev. 2.0 — 14 November 2018
64 / 137
NXP [ NXP ]
