NXP Semiconductors
PF4210
14-channel power management integrated circuit (PMIC) for audio/video applications
Register
Address
0x3D
0x3E
0x3F
0x40
0x43
0x44
0x45
0x46
0x47
Output
SW3ASTBY
SW3AOFF
SW3AMODE
SW3ACONF
SW3BVOLT
SW3BSTBY
SW3BOFF
SW3BMODE
SW3BCONF
SW3A output voltage set point on standby
SW3A output voltage set point on sleep
SW3A switching mode selector register
SW3A DVS, phase, frequency and ILIM configuration
SW3B output voltage set point on normal operation
SW3B output voltage set point on standby
SW3B output voltage set point on sleep
SW3B switching mode selector register
SW3B DVS, phase, frequency and ILIM configuration
Table 65.ꢀRegister SW3AVOLT - ADDR 0x3C
Name
Bit number
R/W
Default Description
SW3A
5:0
R/W
0x00
Sets the SW3A output voltage (independent) or SW3A/B
output voltage (single/dual phase), during normal operation
mode. See Table 63 for all possible configurations.
SW3A
6
7
R
0x00
Sets the operating output voltage range for SW3A
(independent) or SW3A/B (single/dual phase). Set during
OTP or TBB configuration only. See Table 63 for all possible
configurations.
UNUSED
—
0x00
unused
Table 66.ꢀRegister SW3ASTBY - ADDR 0x3D
Name
Bit number
R/W
Default Description
SW3ASTBY
5:0
R/W
0x00
Sets the SW3A output voltage (independent) or SW3A/B
output voltage (single/dual phase), during standby mode. See
Table 63 for all possible configurations.
SW3ASTBY
UNUSED
6
7
R
0x00
Sets the operating output voltage range for SW3A
(independent) or SW3A/B (single/dual phase) in standby
mode. This bit inherits the value configured on bit SW3A[6]
during OTP or TBB configuration. See Table 63 for all
possible configurations.
—
0x00
unused
Table 67.ꢀRegister SW3AOFF - ADDR 0x3E
Name
Bit number
R/W
Default Description
0x00 Sets the SW3A output voltage (independent) or SW3A/B
SW3AOFF
5:0
R/W
output voltage (single/dual phase), during sleep mode. See
Table 63 for all possible configurations.
PF4210
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© NXP B.V. 2018. All rights reserved.
Data sheet: technical data
Rev. 2.0 — 14 November 2018
67 / 137
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