NXP Semiconductors
PF4210
14-channel power management integrated circuit (PMIC) for audio/video applications
Table 71.ꢀRegister SW3BSTBY - ADDR 0x44
Name
Bit number
R/W
Default Description
SW3BSTBY
5:0
R/W
0x00
Sets the SW3B output voltage (independent) during standby
mode. See Table 63 for all possible configurations.
SW3BSTBY
UNUSED
6
7
R
0x00
Sets the operating output voltage range for SW3B
(independent) in standby mode. This bit inherits the value
configured on bit SW3B[6] during OTP or TBB configuration.
See Table 63 for all possible configurations.
—
0x00
unused
Table 72.ꢀRegister SW3BOFF - ADDR 0x45
Name
Bit number
R/W
Default Description
SW3BOFF
5:0
R/W
0x00
Sets the SW3B output voltage (independent) during sleep
mode. See Table 63 for all possible configurations.
SW3BOFF
UNUSED
6
7
R
0x00
Sets the operating output voltage range for SW3B
(independent) in sleep mode. This bit inherits the value
configured on bit SW3B[6] during OTP or TBB configuration.
See Table 63 for all possible configurations.
—
0x00
unused
Table 73.ꢀRegister SW3BMODE - ADDR 0x46
Name
Bit number
R/W
Default Description
SW3BMODE
3:0
R/W
0x08
Sets the SW3B (independent) switching operation mode. See
Table 29 for all possible configurations.
UNUSED
4
5
—
0x00
0x00
unused
SW3BOMODE
R/W
Set status of SW3B (independent) when in sleep mode.
• 0 = OFF
• 1 = PFM
UNUSED
7:6
—
0x00
unused
Table 74.ꢀRegister SW3BCONF - ADDR 0x47
Name
Bit number
R/W
Default Description
SW3BILIM
0
R/W
0x00
SW3B current limit level selection
• 0 = High-level Current limit
• 1 = Low-level Current limit
UNUSED
1
R/W
R/W
R/W
R/W
0x00
0x00
0x00
0x00
unused
SW3BFREQ
SW3BPHASE
SW3BDVSSPEED
3:2
5:4
7:6
SW3B switching frequency selector. See Table 36.
SW3B phase clock selection. See Table 34.
SW3B DVS speed selection. See Table 33.
PF4210
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© NXP B.V. 2018. All rights reserved.
Data sheet: technical data
Rev. 2.0 — 14 November 2018
69 / 137
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