NXP Semiconductors
PF4210
14-channel power management integrated circuit (PMIC) for audio/video applications
aaa-027177
100
efficiency
(%)
APS
PWM
80
60
40
20
0
10
100
1000
10000
load current (mA)
Figure 19.ꢀSW2 efficiency waveforms: vIN = 4.2 V; Vout = 3.0 V; industrial version
10.4.4.5 SW3A/B
SW3A/B are 1.5 to 3.0 A rated buck regulators, depending on the configuration.
Table 28 describes the available switching modes and Table 29 shows the actual
configuration options for the SW3xMODE[3:0] bits. SW3A/B can be configured in various
phasing schemes, depending on the desired cost/performance trade-offs. The following
configurations are available:
• A single phase
• A dual phase
• Independent regulators
The desired configuration is programmed in OTP by using the SW3_CONFIG[1:0] bits.
Table 62 shows the options for the SW3CFG[1:0] bits.
Table 62.ꢀSW3 configuration
SW3_CONFIG[1:0]
Description
00
01
10
11
A/B single phase
A/B single phase
A/B dual phase
A/B independent
10.4.4.5.1 SW3A/B single phase
In this configuration, SW3ALX and SW3BLX are connected in single phase with a
single inductor a shown in Figure 20. This configuration reduces cost and component
count. Feedback is taken from the SW3AFB pin and the SW3BFB pin must be left open.
Although control is from SW3A, registers of both regulators, SW3A and SW3B, must be
identically set.
PF4210
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© NXP B.V. 2018. All rights reserved.
Data sheet: technical data
Rev. 2.0 — 14 November 2018
61 / 137
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