NXP Semiconductors
PF4210
14-channel power management integrated circuit (PMIC) for audio/video applications
Table 30.ꢀDVS control logic for SW1A/B/C
STANDBY
Set point selected by
SW1x[5:0]
0
1
SW1xSTBY[5:0]
Table 31.ꢀDVS control logic for SW2, SW3A/B, and SW4
STANDBY
Set point selected by
0
1
SWx[6:0]
SWxSTBY[6:0]
Table 32.ꢀDVS speed selection for SW1A/B/C
SW1xDVSSPEED[1:0]
Function
00
25 mV step each 2.0 µs
25 mV step each 4.0 µs
25 mV step each 8.0 µs
25 mV step each 16 µs
01 (default)
10
11
Table 33.ꢀDVS speed selection for SW2, SW3A/B, and SW4
SWxDVSSPEED[1:0]
Function
Function
SWx[6] = 0 or SWxSTBY[6] = SWx[6] = 1 or SWxSTBY[6] =
0
1
00
25 mV step each 2.0 µs
25 mV step each 4.0 µs
25 mV step each 8.0 µs
25 mV step each 16 µs
50 mV step each 4.0 µs
50 mV step each 8.0 µs
50 mV step each 16 µs
50 mV step each 32 µs
01 (default)
10
11
The regulators have a strong sourcing and sinking capability in PWM mode, therefore the
fastest rising and falling slopes are determined by the regulator in PWM mode. However,
if the regulators are programmed in PFM or APS mode during a DVS transition, the
falling slope can be influenced by the load. Additionally, as the current capability in PFM
mode is reduced, controlled DVS transitions in PFM mode could be affected. Critically
timed DVS transitions are best assured with PWM mode operation.
The following diagram shows the general behavior for the regulators when initiated with
I2C programming, or standby control. During the DVS period the overcurrent condition of
the regulator should be masked.
PF4210
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© NXP B.V. 2018. All rights reserved.
Data sheet: technical data
Rev. 2.0 — 14 November 2018
35 / 137
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