NXP Semiconductors
PF4210
14-channel power management integrated circuit (PMIC) for audio/video applications
Requested
set point
Output voltage
with light load
Internally
controlled steps
Example
actual output
voltage
Output
voltage
Initial
set point
Actual
output voltage
Internally
controlled steps
Possible
output voltage
window
Request for
higher voltage
Request for
lower voltage
Voltage
change
request
2
Initiated by I C programming, standby control
aaa-026478
Figure 9.ꢀVoltage stepping with DVS
10.4.4.2.2 Regulator phase clock
The SWxPHASE[1:0] bits select the phase of the regulator clock as shown in Table 34.
By default, each regulator is initialized at 90 ° out of phase with respect to each other. For
example, SW1x is set to 0 °, SW2 is set to 90 °, SW3A/B is set to 180 °, and SW4 is set
to 270 ° by default at power up.
Table 34.ꢀRegulator phase clock selection
SWxPHASE[1:0]
Phase of clock sent to regulator (degrees)
00
01
10
11
0
90
180
270
The SWxFREQ[1:0] register is used to set the desired switching frequency for each
one of the buck regulators. Table 36 shows the selectable options for SWxFREQ[1:0].
For each frequency, all phases are available, allowing regulators operating at different
frequencies to have different relative switching phases. However, not all combinations
are practical. For example, 2.0 MHz, 90 ° and 4.0 MHz, 180 ° are the same in terms of
phasing. Table 35 shows the optimum phasing when using more than one switching
frequency.
Table 35.ꢀOptimum phasing
Frequencies
Optimum phasing
1.0 MHz
2.0 MHz
0 °
180 °
1.0 MHz
4.0 MHz
0 °
180 °
2.0 MHz
4.0 MHz
0 °
180 °
1.0 MHz
2.0 MHz
4.0 MHz
0 °
90 °
90 °
PF4210
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© NXP B.V. 2018. All rights reserved.
Data sheet: technical data
Rev. 2.0 — 14 November 2018
36 / 137
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