NXP Semiconductors
PF4210
14-channel power management integrated circuit (PMIC) for audio/video applications
Regulators
Control bits
% of power stages
enabled
Rated current (A)
0
0
1
1
0
1
0
1
1
1
1
1
40 %
80 %
60 %
100 %
0.5
1.0
0.75
1.5
SW4
SW4_PWRSTG[2:0]
ISW4MAX
0.5
0
0
1
1
0
1
0
1
1
1
1
1
50 %
75 %
75 %
100 %
0.75
0.75
1.0
10.4.4.3 SW1A/B/C
SW1/A/B/C are 2.5 A to 4.5 A buck regulators which can be configured in various
phasing schemes, depending on the desired cost/ performance trade-offs. The following
configurations are available:
• SW1A/B/C single phase with one inductor
• SW1A/B as a single phase with one inductor and SW1C in independent mode with one
inductor
• SW1A/B as a dual phase with two inductors and SW1C in independent mode with one
inductor
The desired configuration is programmed by OTP by using SW1_CONFIG[1:0] bits in the
register map Table 135, as shown in Table 38.
Table 38.ꢀSW1 configuration
SW1_CONFIG[1:0]
Description
00
01
10
11
A/B/C single phase
A/B single phase, C independent mode
A/B dual phase, C independent mode
Reserved
10.4.4.3.1 SW1A/B/C single phase
In this configuration, all phases A, B, and C are connected together to a single inductor,
thus, providing up to 4.50 A current capability for high current applications. The feedback
and all other controls are accomplished by use of pin SW1CFB and SW1C control
registers, respectively. Figure 10 shows the connection for SW1A/B/C in single phase
mode.
During single phase mode operation, all three phases use the same configuration for
frequency, phase, and DVS speed set in SW1CCONF register. However, the same
configuration settings for frequency, phase, and DVS speed setting on SW1AB registers
should be used. The SW1FB pin should be left floating in this configuration.
PF4210
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© NXP B.V. 2018. All rights reserved.
Data sheet: technical data
Rev. 2.0 — 14 November 2018
38 / 137
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