NXP Semiconductors
PF4210
14-channel power management integrated circuit (PMIC) for audio/video applications
Table 36.ꢀRegulator frequency configuration
SWxFREQ[1:0]
Frequency
1.0 MHz
00
01
10
11
2.0 MHz
4.0 MHz
Reserved
10.4.4.2.3 Programmable maximum current
The maximum current, ISWxMAX, of each buck regulator is programmable. This allows
the use of smaller inductors where lower currents are required. Programmability is
accomplished by choosing the number of paralleled power stages in each regulator. The
SWx_PWRSTG[2:0] bits in Table 136 of the register map control the number of power
stages.
See Table 37 for the programmable options. Bit[0] must always be enabled to ensure the
stage with the current sensor is used. The default setting, SWx_PWRSTG[2:0] = 111,
represents the highest maximum current. The current limit for each option is also scaled
by the percentage of power stages enabled.
Table 37.ꢀProgrammable current configuration
Regulators
Control bits
% of power stages
enabled
Rated current (A)
SW1AB
SW1AB_PWRSTG[2:0]
ISW1ABMAX
1.0
0
0
1
1
0
1
0
1
1
1
1
1
40 %
80 %
60 %
100 %
2.0
1.5
2.5
SW1C
SW1C_PWRSTG[2:0]
ISW1CMAX
0.9
0
0
1
1
0
1
0
1
1
1
1
1
43 %
58 %
86 %
100 %
1.2
1.7
2.0
SW2
SW2_PWRSTG[2:0]
ISW2MAX
0.75
0
0
1
1
0
1
0
1
1
1
1
1
38%
75%
1.5
63 %
100 %
1.25
2.5
SW3A
SW3B
SW3A_PWRSTG[2:0]
ISW3AMAX
0.5
0
0
1
1
0
1
0
1
1
1
1
1
40 %
80 %
60 %
100 %
1.0
0.75
1.5
SW3B_PWRSTG[2:0]
ISW3BMAX
PF4210
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© NXP B.V. 2018. All rights reserved.
Data sheet: technical data
Rev. 2.0 — 14 November 2018
37 / 137
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