NXP Semiconductors
PF4210
14-channel power management integrated circuit (PMIC) for audio/video applications
BITS[7:0]
Add
Register name R/W
Default
7
6
5
4
3
x
x
x
x
x
2
x
x
x
x
x
1
0
x
x
x
x
x
6D
VGEN2CTL
VGEN3CTL
VGEN4CTL
VGEN5CTL
VGEN6CTL
R/W
R/W
R/W
R/W
R/W
8'b000x_
xxxx
—
VGEN2LPW VGEN2STBY
R
VGEN2EN
VGEN2[3:0]
0
0
0
x
x
6E
6F
70
71
8'b000x_
xxxx
—
VGEN3LPW VGEN3STBY
R
VGEN3EN
VGEN3[3:0]
0
0
0
x
x
8'b000x_
xxxx
—
VGEN4LPW VGEN4STBY
R
VGEN4EN
VGEN4[3:0]
0
0
0
x
x
8'b000x_
xxxx
—
VGEN5LPW VGEN5STBY
R
VGEN5EN
VGEN5[3:0]
0
0
0
x
x
8'b000x_
xxxx
—
VGEN6LPW VGEN6STBY
R
VGEN6EN
VGEN6[3:0]
0
0
0
x
x
7F
Page Register
R/W
8'b0000_
0000
—
0
—
0
—
0
PAGE[4:0]
0
0
0
0
0
Table 135.ꢀExtended page 1
Address
Register name
TYPE
Default
BITS[7:0]
7
6
5
4
3
2
1
0
80
OTP FUSE
READ
R/W
8'b000x_
xxx0
—
—
—
—
—
—
—
OTP FUSE
READ EN
EN
0
0
0
x
x
x
x
0
84
OTP LOAD
MASK
R/W
8'b0000_
0000
START
0
RL PWBRTN FORCE
PWRCTL
RL PWRCTL RL OTP
RL OTP
ECC
RL OTP
FUSE
RL TRIM
FUSE
0
0
0
0
0
0
0
8A
8B
8C
8D
OTP ECC SE1
OTP ECC SE2
OTP ECC DE1
OTP ECC DE2
R
R
R
R
8'bxxx0_
0000
—
x
—
x
—
x
ECC5_SE
ECC4_SE
ECC3_SE
ECC2_SE
ECC1_SE
0
0
0
0
0
8'bxxx0_
0000
—
x
—
x
—
x
ECC10_SE
ECC9_SE
ECC8_SE
ECC7_SE
ECC6_SE
0
0
0
0
0
8'bxxx0_
0000
—
x
—
x
—
x
ECC5_DE
ECC4_DE
ECC3_DE
ECC2_DE
ECC1_DE
0
0
0
0
0
8'bxxx0_
0000
—
x
—
x
—
x
ECC10_DE
0
ECC9_DE
0
ECC8_DE
0
ECC7_DE
0
ECC6_DE
0
A0
A1
A2
OTP SW1AB
VOLT
R/W
R/W
R/W
8'b00xx_xxxx
—
0
—
0
SW1AB_VOLT[5:0]
x
x
x
x
x
x
x
x
OTP SW1AB
SEQ
8'b000x_
xxXx
—
0
SW1AB_SEQ[4:0]
x
0
0
x
X
OTP SW1AB
CONFIG
8'b0000_
xxxx
—
0
—
0
—
0
—
0
SW1_CONFIG[1:0]
SW1AB_FREQ[1:0]
x
x
x
x
A8
A9
AA
OTP SW1C
VOLT
R/W
8'b00xx_xxxx
8'b000x_xxxx
—
0
—
0
SW1C_VOLT[5:0]
x
x
x
x
x
x
x
x
OTP SW1C SEQ R/W
—
0
SW1C_SEQ[4:0]
0
0
x
x
x
x
OTP SW1C
CONFIG
R/W
8'b0000_
00xx
—
0
—
0
—
0
—
0
—
0
—
0
SW1C_FREQ[1:0]
x
PF4210
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2018. All rights reserved.
Data sheet: technical data
Rev. 2.0 — 14 November 2018
117 / 137
NXP [ NXP ]
