NXP Semiconductors
PF4210
14-channel power management integrated circuit (PMIC) for audio/video applications
R/W: Read / Write access and control
• R is read-only access
• R/W is read and write access
• RW1C is read and write access with write 1 to clear
Reset: Reset signals are color coded based on the following legend.
Bits reset by SC and VCOREDIG_PORB
Bits reset by PWRON or loaded default or OTP configuration
Bits reset by DIGRESETB
Bits reset by PORB or RESETBMCU
Bits reset by VCOREDIG_PORB
Bits reset by POR or OFFB
Default: The value after reset, as noted in the default column of the memory map.
• Fixed defaults are explicitly declared as 0 or 1
• X corresponds to read/write bits that are initialized at startup, based on the OTP fuse
settings or default if VDDOTP = 1.5 V. Bits are subsequently I2C modifiable, when their
reset has been released. X may also refer to bits which may have other dependencies.
For example, some bits may depend on the version of the IC, or a value from an analog
block, for instance the sense bits for the interrupts.
10.7.1 Register map
Table 134.ꢀFunctional page
BITS[7:0]
Add
Register name R/W
Default
7
6
5
4
3
2
1
0
00
DeviceID
R
8'b0001_
0000
—
0
—
0
—
0
—
1
DEVICE ID [3:0]
0
0
0
0
03
04
05
06
07
08
09
SILICONREVID
FABID
R
R
8'b0001_
0000
FULL_LAYER_REV[3:0]
METAL_LAYER_REV[3:0]
x
x
x
x
x
x
x
FAB[1:0]
0
x
8'b0000_
0000
—
0
—
0
—
—
FIN[1:0]
0
0
0
0
0
INTSTAT0
INTMASK0
INTSENSE0
INTSTAT1
INTMASK1
RW
1C
8'b0000_
0000
—
0
—
0
THERM130I
THERM125I
0
THERM120I
0
THERM110I
0
LOWVINI
0
PWRONI
0
0
R/W
R
8'b0011_
1111
—
0
—
0
THERM130M
1
THERM125M THERM120M THERM110M LOWVINM
PWRONM
1
1
1
1
1
8'b00xx_xxxx VDDOTPS
0
RSVD
0
THERM130S
x
THERM125S THERM120S THERM110S LOWVINS
PWRONS
x
x
x
x
x
RW
1C
8'b0000_
0000
—
0
SW4FAULTI SW3BFAULTI
SW3AFAULTI SW2FAULTI
SW1CFAULTI SW1BFAULTI
SW1AFAULTI
0
0
0
0
0
0
0
R/W
8'b0111_
1111
—
SW4FAULT
M
SW3BFAULTM SW3AFAUL
TM
SW2FAULTM SW1CFAUL
TM
SW1BFAULTM SW1AFAULTM
0
1
1
1
1
1
1
1
0A
INTSENSE1
INTSTAT3
R
8'b0xxx_xxxx
—
SW4FAULTS SW3BFAULTS SW3AFAUL
TS
SW2FAULTS SW1CFAUL
TS
SW1BFAULTS SW1AFAULTS
0
x
x
x
x
x
x
x
0E
RW
1C
8'b0000_
0000
OTP_ECCI
0
—
0
—
0
—
0
—
0
—
0
—
0
SWBSTFAULTI
0
PF4210
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© NXP B.V. 2018. All rights reserved.
Data sheet: technical data
Rev. 2.0 — 14 November 2018
114 / 137
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