NXP Semiconductors
PF4210
14-channel power management integrated circuit (PMIC) for audio/video applications
Name
Bit number
R/W
Default Description
0x00 unused
Unused
7:0
R
10.6.2 Embedded memory
There are four register banks of general purpose embedded memory to store critical
data. The data written to MEMA[7:0], MEMB[7:0], MEMC[7:0], and MEMD[7:0] is
maintained by the coin cell when the main battery is deeply discharged, removed, or
contact-bounced. The contents of the embedded memory are reset by COINPORB. The
banks can be used for any system need for bit retention with coin cell backup.
Table 130.ꢀRegister MEMA ADDR 0x1C
Name
Bit number
R/W
Default Description
0 Memory bank A
MEMA
7:0
R/W
Table 131.ꢀRegister MEMB ADDR 0x1D
Name
Bit number
R/W
Default Description
0 Memory bank B
MEMB
7:0
R/W
Table 132.ꢀRegister MEMC ADDR 0x1E
Name
Bit number
R/W
Default Description
0 Memory bank C
MEMC
7:0
R/W
Table 133.ꢀRegister MEMD ADDR 0x1F
Name
Bit number
R/W
Default Description
0 Memory bank D
MEMD
7:0
R/W
10.7 Register bitmap
The register map is comprised of thirty-two pages, and its address and data fields are
each eight bits wide. Only the first two pages can be accessed. On each page, registers
0 to 0x7F are referred to as functional, and registers 0x80 to 0xFF as extended. On each
page, the functional registers are the same, but the extended registers are different.
To access registers in Table 135, write 0x01 to the page register at address 0x7F, and
to access registers in Table 136, write 0x02 to the page register at address 0x7F. To
access Table 134, from one of the extended pages, no write to the page register is
necessary.
Registers missing in the sequence are reserved; reading from them returns a value 0x00,
and writing to them has no effect.
The contents of all registers are given in the tables defined in this chapter. Each table is
structured as follows:
Name: Name of the bit.
Bit number: The bit location in the register (7-0)
PF4210
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Data sheet: technical data
Rev. 2.0 — 14 November 2018
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