NXP Semiconductors
PF4210
14-channel power management integrated circuit (PMIC) for audio/video applications
Address
D0
Register name
TYPE
R/W
Default
BITS[7:0]
7
6
5
4
3
x
x
2
1
0
x
x
OTP VGEN3
VOLT
8'b0000_
xxxx
—
0
—
0
—
0
—
0
VGEN3_VOLT[3:0]
x
x
D1
OTP VGEN3
SEQ
R/W
8'b000x_xxxx
—
0
—
0
—
0
VGEN3_SEQ[4:0]
x
x
x
D4
D5
OTP VGEN4
VOLT
R/W
R/W
8'b0000_
xxxx
—
0
—
0
—
0
—
0
VGEN4_VOLT[3:0]
x
x
x
x
x
x
OTP VGEN4
SEQ
8'b000x_xxxx
—
0
—
0
—
0
VGEN4_SEQ[4:0]
x
x
x
D8
D9
OTP VGEN5
VOLT
R/W
R/W
8'b0000_
xxxx
—
0
—
0
—
0
—
0
VGEN5_VOLT[3:0]
x
x
x
x
x
x
OTP VGEN5
SEQ
8'b000x_xxxx
—
0
—
0
—
0
VGEN5_SEQ[4:0]
x
x
x
DC
DD
OTP VGEN6
VOLT
R/W
R/W
8'b0000_
xxxx
—
0
—
0
—
0
—
0
VGEN6_VOLT[3:0]
x
x
x
x
x
OTP VGEN6
SEQ
8'b000x_xxxx
—
0
—
0
—
0
VGEN6_SEQ[4:0]
x
x
x
x
E0
OTP PU
CONFIG1
R/W
R/W
R/W
R
8'b000x_xxxx
8'b000x_xxxx
8'b000x_xxxx
8'b000x_xxxx
—
—
—
PWRON_
CFG1
SWDVS_CLK1[1:0]
SEQ_CLK_SPEED1[1:0]
0
0
0
x
x
x
x
x
x
x
x
x
x
E1
OTP PU
CONFIG2
—
—
—
PWRON_
CFG2
SWDVS_CLK2[1:0]
SEQ_CLK_SPEED2[1:0]
0
0
0
x
x
x
E2
OTP PU
CONFIG3
—
—
—
PWRON_
CFG3
SWDVS_CLK3[1:0]
SEQ_CLK_SPEED3[1:0]
0
0
0
x
x
x
E3
OTP PU CONFIG
XOR
—
—
—
PWRON_
CFG_XOR
SWDVS_CLK3_XOR
SEQ_CLK_SPEED_XOR
0
0
0
x
x
x
x
E4 [1]
OTP FUSE
POR1
R/W
8'b0000_
00x0
TBB_POR
SOFT_
FUSEPOR
—
—
—
—
FUSE_POR1
–
0
0
0
0
0
0
x
0
–
0
–
0
–
E5
E6
E7
OTP FUSE
POR1
R/W
R/W
R
8'b0000_
00x0
RSVD
0
RSVD
0
—
0
—
0
—
0
—
0
FUSE_POR2
x
OTP FUSE
POR1
8'b0000_
00x0
RSVD
0
RSVD
0
—
0
—
0
—
0
—
0
FUSE_POR3
x
OTP FUSE POR
XOR
8'b0000_
00x0
RSVD
RSVD
—
—
—
—
FUSE_POR_
X
OR
0
0
0
0
0
0
x
0
E8
OTP PWRGD EN R/W/M 8'b0000_
000x
—
—
—
—
—
—
—
OTP_PG_
EN
0
0
0
0
0
0
x
0
F0
F1
F4
OTP EN ECCO
OTP EN ECC1
R/W
R/W
8'b000x_xxxx
8'b000x_xxxx
—
—
—
EN_ECC_
BANK5
EN_ECC_
BANK4
EN_ECC_
BANK3
EN_ECC_
BANK2
EN_ECC_
BANK1
0
0
0
x
x
x
x
x
—
—
—
EN_ECC_
BANK10
EN_ECC_
BANK9
EN_ECC_
BANK8
EN_ECC_
BANK7
EN_ECC_
BANK6
0
0
0
x
x
x
x
x
OTP SPARE2_4 R/W
8'b0000_
xxxx
—
0
—
0
—
0
—
0
RSVD
x
x
x
x
PF4210
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2018. All rights reserved.
Data sheet: technical data
Rev. 2.0 — 14 November 2018
119 / 137
NXP [ NXP ]
