NXP Semiconductors
PF4210
14-channel power management integrated circuit (PMIC) for audio/video applications
Address
Register name
TYPE
Default
BITS[7:0]
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
D1
OTP AUTO ECC1 R/W
8'b0000_
0000
—
—
—
AUTO_
ECC_
BANK10
AUTO_
AUTO_
AUTO_
AUTO_
ECC_BANK9 ECC_BANK8 ECCBANK7 ECC_
BANK6
0
0
0
0
0
0
0
0
D8 [1]
D9 [1]
Reserved
Reserved
—
—
8'b0000_
0000
RSVD
0
0
0
0
0
0
0
0
0
0
0
0
0
0
8'b0000_
0000
RSVD
0
0
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
OTP ECC CTRL1 R/W
OTP ECC CTRL2 R/W
OTP ECC CTRL3 R/W
OTP ECC CTRL4 R/W
OTP ECC CTRL5 R/W
OTP ECC CTRL6 R/W
OTP ECC CTRL7 R/W
OTP ECC CTRL8 R/W
OTP ECC CTRL9 R/W
8'b0000_
0000
ECC1_EN_
TBB
ECC1_
CALC_CIN
ECC1_CIN_TBB[5:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
8'b0000_
0000
ECC2_EN_
TBB
ECC2_
CALC_CIN
ECC2_CIN_TBB[5:0]
0
0
0
8'b0000_
0000
ECC3_EN_
TBB
ECC3_
CALC_CIN
ECC3_CIN_TBB[5:0]
0
0
0
8'b0000_
0000
ECC4_EN_
TBB
ECC4_
CALC_CIN
ECC4_CIN_TBB[5:0]
0
0
0
8'b0000_
0000
ECC5_EN_
TBB
ECC5_
CALC_CIN
ECC5_CIN_TBB[5:0]
0
0
0
8'b0000_
0000
ECC6_EN_
TBB
ECC6_
CALC_CIN
ECC6_CIN_TBB[5:0]
0
0
0
8'b0000_
0000
ECC7_EN_
TBB
ECC7_
CALC_CIN
ECC7_CIN_TBB[5:0]
0
0
0
8'b0000_
0000
ECC8_EN_
TBB
ECC8_
CALC_CIN
ECC8_CIN_TBB[5:0]
0
0
0
8'b0000_
0000
ECC9_EN_
TBB
ECC9_
CALC_CIN
ECC9_CIN_TBB[5:0]
0
0
0
OTP ECC
CTRL10
R/W
8'b0000_
0000
ECC10_EN_ ECC10_
TBB
ECC10_CIN_TBB[5:0]
CALC_CIN
0
0
0
0
0
F1
F2
F3
F4
F5
OTP FUSE
CTRL1
R/W
R/W
R/W
R/W
R/W
8'b0000_
0000
—
—
—
—
ANTIFUSE1_ ANTIFUSE1_ ANTIFUSE1_ BYPASS1
EN
LOAD
RW
0
0
0
0
0
0
0
0
OTP FUSE
CTRL2
8'b0000_
0000
—
—
—
—
ANTIFUSE2_ ANTIFUSE2_ ANTIFUSE2_ BYPASS2
EN
LOAD
RW
0
0
0
0
0
0
0
0
OTP FUSE
CTRL3
8'b0000_
0000
—
—
—
—
ANTIFUSE3_ ANTIFUSE3_ ANTIFUSE3_ BYPASS3
EN
LOAD
RW
0
0
0
0
0
0
0
0
OTP FUSE
CTRL4
8'b0000_
0000
—
—
—
—
ANTIFUSE4_ ANTIFUSE4_ ANTIFUSE4_ BYPASS4
EN
LOAD
RW
0
0
0
0
0
0
0
0
OTP FUSE
CTRL5
8'b0000_
0000
—
—
—
—
ANTIFUSE5_ ANTIFUSE5_ ANTIFUSE5_ BYPASS5
EN
LOAD
RW
0
0
0
0
0
0
0
0
PF4210
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2018. All rights reserved.
Data sheet: technical data
Rev. 2.0 — 14 November 2018
121 / 137
NXP [ NXP ]
