NXP Semiconductors
PF4210
14-channel power management integrated circuit (PMIC) for audio/video applications
Address
Register name
TYPE
Default
BITS[7:0]
7
6
5
4
3
2
1
0
F5
F6
F7
OTP SPARE4_3 R/W
OTP SPARE6_2 R/W
OTP SPARE7_1 R/W
8'b0000_
0xxx
—
0
—
0
—
0
—
0
—
0
RSVD
x
x
x
RSVD
x
8'b0000_
00xx
—
0
—
0
—
0
—
0
—
0
—
0
x
8'b0000_
0xxx
—
0
—
0
—
0
—
0
—
0
—
x
—
x
RSVD
x
FE
FF
OTP DONE
R/W
R/W
8'b0000_
000x
—
0
—
0
—
0
—
0
—
0
—
0
—
0
OTP_DONE
x
OTP I2C ADDR
8'b0000_
0xxx
—
—
—
—
I2C_SLV
ADDR[3]
I2C_SLV ADDR[2:0]
0
0
0
0
1
x
x
x
[1] In the PF4210 FUSE_POR1, FUSE_POR2, and FUSE_POR3 are XOR'ed into the FUSE_POR_XOR bit. The FUSE_POR_XOR has to be 1 for fuses to
be loaded. This can be achieved by setting any one or all of the FUSE_PORx bits. In PF4210, the XOR function is removed. It is required to set all of the
FUSE_PORx bits to be able to load the fuses.
Table 136.ꢀExtended Page 2
Address
Register name
TYPE
Default
BITS[7:0]
7
6
5
4
3
2
1
0
81
82
83
84
85
86
87
SW1AB PWRSTG R/W
8'b1111_
1111
RSVD
1
RSVD
1
RSVD
1
RSVD
1
RSVD
1
SW1AB_PWRSTG[2:0]
1
0
1
1
1
1
1
1
PWRSTG RSVD
SW1C PWRSTG
SW2 PWRSTG
SW3A PWRSTG
SW3B PWRSTG
SW4 PWRSTG
R
R
R
R
R
R
8'b0000_
0000
PWRSTGRSVD
0
0
0
0
0
0
0
8'b1111_
1111
RSVD
RSVD
RSVD
1
RSVD
1
RSVD
1
SW1C_PWRSTG[2:0]
1
1
1
1
8'b1111_
1111
RSVD
RSVD
RSVD
1
RSVD
1
RSVD
1
SW2_PWRSTG[2:0]
1
1
1
1
8'b1111_
1111
RSVD
RSVD
RSVD
1
RSVD
1
RSVD
1
SW3A_PWRSTG[2:0]
1
1
1
1
8'b1111_
1111
RSVD
1
RSVD
1
RSVD
1
RSVD
1
RSVD
1
SW3B_PWRSTG[2:0]
1
1
8'b0111_
1111
FSLEXT_
THERM_
DISABLE
PWRGD_
SHDWN_
DISABLE
RSVD
RSVD
RSVD
SW4_PWRSTG[2:0]
0
0
1
1
1
1
1
1
88
PWRCTRL OTP
CTRL
R/W
8'b0000_
0001
—
—
—
—
—
—
PWRGD_EN OTP_
SHDWN_EN
0
0
0
0
0
0
0
0
0
0
1
8D
8E
I2C WRITE
R/W
R/W
8'b0000_
0000
I2C_WRITE_ADDRESS_TRAP[7:0]
ADDRESS TRAP
0
0
0
0
0
0
I2C TRAP PAGE
8'b0000_
0000
LET_IT_
ROLL
RSVD
RSVD
I2C_TRAP_PAGE[4:0]
0
0
0
0
0
–
0
0
x
–
0
0
0
0
0
x
8F
90
I2C TRAP CNTR
IO DRV
R/W
R/W
8'b0000_
0000
I2C_WRITE_ADDRESS_COUNTER[7:0]
0
0
0
0
8'b00xx_xxxx
SDA_DRV[1:0]
SDWNB_DRV[1:0]
x
INTB_DRV[1:0]
x
RESETBMCU_DRV[1:0]
x
0
x
DO
OTP AUTO ECC0 R/W
8'b0000_
0000
—
AUTO_
AUTO_
AUTO_
AUTO_
AUTO_
ECC_BANK5 ECC_BANK4 ECC_BANK3 ECC_BANK2 ECC_
BANK1
PF4210
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© NXP B.V. 2018. All rights reserved.
Data sheet: technical data
Rev. 2.0 — 14 November 2018
120 / 137
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