NXP Semiconductors
PF4210
14-channel power management integrated circuit (PMIC) for audio/video applications
10.4.6.7.2 External components
Table 112.ꢀCoin cell charger external components
Component
Value
Units
LICELL bypass capacitor
100
nF
10.4.6.7.3 Coin cell specifications
Table 113.ꢀCoin cell charger specifications
Parameter
Typ
Unit
Voltage accuracy
100
60
mV
µA
%
Coin cell charge current in on mode ICOINHI
Current accuracy
30
10.5 Control interface I2C block description
The PF4210 contains an I2C interface port which allows access by a processor, or
any I2C master, to the register set. Via these registers the resources of the IC can be
controlled. The registers also provide status information about how the IC is operating.
The SCL and SDA lines should be routed away from noisy signals and planes to
minimize noise pick up. To prevent reflections in the SCL and SDA traces from creating
false pulses, the rise and fall times of the SCL and SDA signals must be greater than
20 ns. This can be accomplished by reducing the drive strength of the I2C master via
software. Alternatively, this can be accomplished by using small capacitors from SCL and
SDA to ground. For example, use 5.1 pF capacitors from SCL and SDA to ground for bus
pull-up resistors of 4.8 kΩ.
10.5.1 I2C device ID
I2C interface protocol requires a device ID for addressing the target IC on a multi-device
bus. To allow flexibility in addressing for bus conflict avoidance, fuse programmability is
provided to allow configuration for the lower 3 address LSB(s). See Section 10.1.2 "One
time programmability (OTP)" for more details. This product supports 7-bit addressing
only; support is not provided for 10-bit or general call addressing.
Note: When the TBB bits for the I2C slave address are written, the next access to the
chip, must then use the new slave address; these bits take affect right away.
10.5.2 I2C operation
The I2C mode of the interface is implemented generally following the fast mode definition
which supports up to 400 kbits/s operation (exceptions to the standard are noted to be
7-bit only addressing and no support for general call addressing). Timing diagrams,
electrical specifications, and further details can be found in the I2C specification, which is
available for download at:
http://www.nxp.com/acrobat_download/literature/9398/39340011.pdf
I2C read operations are also performed in byte increments separated by an ACK. Read
operations also begin with the MSB and each byte is sent out unless a STOP command
or NACK is received prior to completion.
PF4210
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2018. All rights reserved.
Data sheet: technical data
Rev. 2.0 — 14 November 2018
105 / 137
NXP [ NXP ]
