LPC546xx
NXP Semiconductors
32-bit ARM Cortex-M4 microcontroller
10.4 Power consumption
Power measurements in Active, sleep, and deep-sleep modes were performed under the
following conditions:
• Configure all pins as GPIO with pull-up resistor disabled in the IOCON block.
• Configure GPIO pins as outputs using the GPIO DIR register.
• Write 1 to the GPIO CLR register to drive the outputs LOW.
• All peripherals disabled.
Table 15. Static characteristics: Power consumption in active and sleep mode
Tamb = 40 C to +105 C, unless otherwise specified.1.71 V VDD 3.6 V.
Symbol
Active mode[1]
IDD
Parameter
Conditions
Min
Typ[2]
Max
Unit
supply current
CoreMark code executed from
SRAMX; flash powered down
[3][4][5][7]
[3][4][5][7]
[4][5][7][8]
[4][5][7][8]
CCLK = 12 MHz
-
-
-
-
3.3
11
-
-
-
-
mA
mA
mA
mA
CCLK = 96 MHz
CCLK = 180 MHz
24
30
CCLK = 220 MHz
IDD
supply current
CoreMark code executed from flash;
CCLK = 12 MHz; 1 system clock
flash access time.
[3][4][5][6]
[3][4][5][6]
-
-
4
-
-
mA
mA
CCLK = 96 MHz; 5 system clock
flash access time.
9.4
[4][5][6][8]
[4][5][6][8][9]
[4][5][6][8]
CCLK = 180 MHz; 9 system clock
flash access time.
-
-
-
17
-
-
-
mA
mA
mA
CCLK = 220 MHz; 8 system clock
flash access time.
22.4
21.9
CCLK = 220 MHz; 9 system clock
flash access time.
Sleep mode
[3][4][5][7]
[3][4][5][7]
[4][5][8]
IDD
supply current
CCLK = 12 MHz
CCLK = 96 MHz
CCLK = 180 MHz
-
-
-
1.7
4.1
8.3
-
-
-
mA
mA
mA
[1] Based on the power API library from the SDK software package available on nxp.com.
[2] Typical ratings are not guaranteed. Typical values listed are at room temperature (25 C), 3.3V.
[3] Clock source FRO. PLL disabled.
[4] Characterized through bench measurements using typical samples.
[5] Compiler settings: Keil uVision v.5.21, optimization level 0, optimized for time off.
[6] Acceleration enable bit in the FLASHCFG register is set to 0. SRAM0 powered. SRAM1, SRAM2, SRAM3, USB SRAM and SRAMX
powered down.
[7] Flash is powered down; SRAM0 and SRAMX are powered; SRAM1, SRAM2, SRAM3, and USB SRAM are powered down. All
peripheral clocks disabled.
[8] Clock source FRO. PLL enabled.
[9] At 220 MHz the system clock/access time can be lower when compared to 180 MHz because the power library optimizes the on-chip
voltage regulator.
LPC546xx
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2018. All rights reserved.
Product data sheet
Rev. 2.5 — 20 June 2018
90 of 169
NXP [ NXP ]
