LPC546xx
NXP Semiconductors
32-bit ARM Cortex-M4 microcontroller
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Conditions: VDD = 3.3 V; Tamb = 25 °C; active mode; all peripherals disabled; BOD disabled; See
the FLASHCFG register in the LPC546xx. User Manual for system clock flash access time
settings. Acceleration enable bit in the FLASCFG register is set to 1. Measured with IAR ver
8.22.2. Optimization level 3, optimized for time ON. Coremark score is based on the power API
library from the SDK software package available on nxp.com.
12 MHz, 24 MHz, 48 MHz, and 96 MHz: FRO enabled; PLL disabled.
36 MHz, 60 MHz, 72 MHz, 84 MHz, 108 MHz, 120 MHz, 132 MHz, 144 MHz, 156 MHz, 168 MHz,
180 MHz, 192 MHz, 204 MHz, 216 MHz, and 220 MHz: FRO enabled; PLL enabled.
CoreMark score from flash: SRAM1, SRAM2, SRAM3, and USB SRAM powered down. SRAM0
and SRAMX powered.
CoreMark score from SRAMX: SRAM0 is powered; flash is powered down.
Fig 14. Typical CoreMark score (iterations/s/MHz) vs. Frequency (MHz) from flash and
SRAMX
LPC546xx
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2018. All rights reserved.
Product data sheet
Rev. 2.5 — 20 June 2018
89 of 169
NXP [ NXP ]
