LPC546xx
NXP Semiconductors
32-bit ARM Cortex-M4 microcontroller
APB bridge 1
APB bridge 0
0x4003 FFFF
0x4003 B000
0x4003 A000
0x4003 8000
0x4001 FFFF
0x4001 6000
0x4001 5000
0x4001 4000
0x4001 F000
0x4000 E000
(reserved)
(reserved)
31-27
26
25-24
31-22
21
RNG
(reserved)
OTP controller
20
19-15
14
13
12
11-10
9
EEPROM controller
(reserved)
Smart card 1
Smart card 0
(reserved)
23
22
0x4003 7000
0x4003 6000
Micro-Tick
MRT
21
0x4003 5000
0x4000 D000
0x4000 C000
0x4000 A000
0x4000 9000
0x4000 8000
0x4000 6000
0x4000 5000
0x4000 4000
0x4000 3000
0x4000 2000
0x4000 1000
0x4000 0000
Flash controller
(reserved)
20
19-14
0x4003 4000
0x4002 E000
WDT
(reserved)
CTIMER1
CTIMER0
(reserved)
Input muxes
Pin Interrupts (PINT)
GINT1
RIT
RTC
13
12
0x4002 D000
0x4002 C000
8
(reserved)
11-9
0x4002 9000
7-6
5
CTIMER2
(reserved)
8
7-0
0x4002 8000
0x4002 0000
4
Asynchronous APB bridge
3
0x4005 FFFF
GINT0
2
(reserved)
CTIMER4
31-10
0x4004 A000
0x4004 9000
0x4004 8000
0x4004 1000
0x4004 0000
aaa-023944
IOCON
1
9
8
Syscon
2
CTIMER3
(reserved)
7-1
0
Asynch. Syscon
Fig 10. LPC546xx APB Memory map
7.12 System control
7.12.1 Clock sources
The LPC546xx supports one external and two internal clock sources:
• Free Running Oscillator (FRO).
• Watchdog oscillator (WDOSC).
• Crystal oscillator.
7.12.1.1 Free Running Oscillator (FRO)
The FRO 12 MHz oscillator provides the default clock at reset and provides a clean
system clock shortly after the supply pins reach operating voltage.
• 12 MHz internal FRO oscillator, factory trimmed for accuracy, that can optionally be
used as a system clock as well as other purposes.
• Selectable 48 MHz or 96 MHz FRO oscillator, factory trimmed for accuracy, that can
optionally be used as a system clock as well as other purposes.
7.12.1.2 Watchdog oscillator (WDOSC)
The watchdog oscillator is a low-power internal oscillator. The WDOSC can be used to
provide a clock to the WWDT and to the entire chip. The low-power watchdog oscillator
provides a selectable frequency in the range of 6 kHz to 1.5 MHz. The accuracy of this
clock is limited to 40% over temperature, voltage, and silicon processing variations.
LPC546xx
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2018. All rights reserved.
Product data sheet
Rev. 2.5 — 20 June 2018
60 of 169
NXP [ NXP ]
