LPC546xx
NXP Semiconductors
32-bit ARM Cortex-M4 microcontroller
(1 per Flexcomm)
to systick
main_clk
function clock
main_clk
000
Systick clock
divider
fro_12m
000
001
010
011
100
111
pll_clk
001
fcn_fclk
fro_hf_div
audio_pll_clk
mclk_in
(function clock
of Flexcomm[n])
fro_12m
010
fro_hf
011
SYSTICKCLKDIV
“none”
(up to 10 Flexcomm
Interfaces on these
devices)
FRG CLOCK
frg_clk
“none”
111
DIVIDER
to MCAN0
function clock
main_clk
main_clk
MCAN0 clock
divider
FRGCTRL[15:0]
FRG clock select
FRGCLKSEL[2:0]
FCLKSEL[n]
CAN0CLKDIV
to CLK32K of all Flexcomms
32k_clk
to MCAN1
function clock
MCAN1 clock
divider
main_clk
pll_clk
000
001
010
011
111
to SCTimer/PWM
input clock 7
SCTimer/PWM
Clock Divider
fro_hf
audio_pll_clk
“none”
CAN1CLKDIV
to Smartcard0
function clock
SCTCLKDIV
main_clk
main_clk
Smartcard0
clock divider
SCT clock select
SCTCLKSEL[2:0]
SC0CLKDIV
to Smartcard1
function clock
main_clk
lcdclkin
fro_hf
00
01
10
11
to LCD
Smartcard1
clock divider
(function clock)
LCD CLOCK
DIVIDER
“none”
SC1CLKDIV
LCDCLKDIV
LCD clock select
LCDCLKSEL[1:0]
to ARM Trace
function clock
main_clk
ARM Trace
clock divider
ARMTRACECLKDIV
main_clk
clk_in
wdt_clk
000
001
010
011
100
101
main_clk
pll_clk
usb_pll_clk
000
001
010
011
100
111
fro_hf
pll_clk
usb_pll_clk
to SPIFI
(function clock)
CLKOUT
CLKOUT
SPIFI CLOCK
DIVIDER
DIVIDER
fro_hf
audio_pll_clk
audio_pll_clk
32k_clk
CLKOUTDIV
“none”
110
111
SPIFI CLKDIV
SPIFI clock select
SPIFICLKSEL[2:0]
CLKOUT select
CLKOUTSEL[2:0]
aaa-023923
Fig 12. LPC546xx clock generation (continued)
7.12.6 Brownout detection
The LPC546xx includes a monitor for the voltage level on the VDD pin. If this voltage falls
below a fixed level, the BOD sets a flag that can be polled or cause an interrupt. In
addition, a separate threshold level can be selected to cause chip reset.
7.12.7 Safety
The LPC546xx includes a Windowed WatchDog Timer (WWDT), which can be enabled by
software after reset. Once enabled, the WWDT remains locked and cannot be modified in
any way until a reset occurs.
LPC546xx
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2018. All rights reserved.
Product data sheet
Rev. 2.5 — 20 June 2018
63 of 169
NXP [ NXP ]
