LPC546xx
NXP Semiconductors
32-bit ARM Cortex-M4 microcontroller
7.13 Code security (enhanced Code Read Protection - eCRP)
eCRP is a mechanism that allows the user to enable different features in the security
system. The features are specified using a combination of OTP and flash values. Some
levels are only controlled by either flash or OTP, but the majority have dual control. The
overlap allows higher security by specifying access using OTP bits, which cannot be
changed (except to increase security) while allowing customers who are less concerned
about security the ability to change levels in the flash image.
eCRP is calculated by reading the ECRP from the flash boot sector (offset 0x0000 0020)
and then masking it with the value read from OTP. The OTP bits are more restrictive (that
is, disable access) than equivalent values in flash. Certain aspects of eCRP are only
specified in the OTP (that is, Mass Erase disable), while others are only specified in flash
(that is, Sector Protection count).
For Dual Enhanced images, eCRP is calculated by reading the eCRP from the bootable
image sector. The bootable image is defined as the highest revision image that passes the
required validation methods.
Remark: If the ECRP is set to the most restrictive combination of OTP and the ECRP of
the images, no future factory testing can be performed on the device.
7.14 Power control
The LPC546xx support a variety of power control features. In Active mode, when the chip
is running, power and clocks to selected peripherals can be adjusted for power
consumption. In addition, there are three special modes of processor power reduction with
different peripherals running: sleep mode, deep-sleep mode, and deep power-down mode
that can be activated using the power API library from the LPCOpen software package.
7.14.1 Sleep mode
In sleep mode, the system clock to the CPU is stopped and execution of instructions is
suspended until either a reset or an interrupt occurs. Peripheral functions, if selected to be
clocked can continue operation during Sleep mode and may generate interrupts to cause
the processor to resume execution. Sleep mode eliminates dynamic power used by the
processor itself, memory systems and related controllers, internal buses, and unused
peripherals. The processor state and registers, peripheral registers, and internal SRAM
values are maintained, and the logic levels of the pins remain static.
7.14.2 Deep-sleep mode
In deep-sleep mode, the system clock to the processor is disabled as in sleep mode. All
analog blocks are powered down by default but can be selected to keep running through
the power API if needed as wake-up sources. The main clock and all peripheral clocks are
disabled. The FRO is disabled. The flash memory is put in standby mode.
Deep-sleep mode eliminates all power used by analog peripherals and all dynamic power
used by the processor itself, memory systems and related controllers, and internal buses.
The processor state and registers, peripheral registers, and internal SRAM values are
maintained, and the logic levels of the pins remain static.
LPC546xx
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2018. All rights reserved.
Product data sheet
Rev. 2.5 — 20 June 2018
64 of 169
NXP [ NXP ]
