LPC546xx
NXP Semiconductors
32-bit ARM Cortex-M4 microcontroller
7.5 Nested Vectored Interrupt Controller (NVIC) for Cortex-M4
The NVIC is an integral part of the Cortex-M4. The tight coupling to the CPU allows for low
interrupt latency and efficient processing of late arriving interrupts.
7.5.1 Features
• Controls system exceptions and peripheral interrupts.
• Supports up to 54 vectored interrupts.
• Eight programmable interrupt priority levels, with hardware priority level masking.
• Relocatable vector table.
• Non-Maskable Interrupt (NMI).
• Software interrupt generation.
7.5.2 Interrupt sources
Each peripheral device has one interrupt line connected to the NVIC but may have several
interrupt flags.
7.6 System Tick timer (SysTick)
The ARM Cortex-M4 includes a system tick timer (SysTick) that is intended to generate a
dedicated SYSTICK exception. The clock source for the SysTick can be the FRO or the
Cortex-M4 core clock.
7.7 On-chip static RAM
The LPC546xx support 200 kB SRAM with separate bus master access for higher
throughput and individual power control for low-power operation.
7.8 On-chip flash
The LPC546xx supports up to 512 kB of on-chip flash memory.
7.9 On-chip ROM
The 64 kB on-chip ROM contains the boot loader and the following Application
Programming Interfaces (API):
• Flash In-Application Programming (IAP) and In-System Programming (ISP).
• ROM-based USB drivers (HID, CDC, MSC, and DFU). Supports flash updates via
USB.
• Supports booting from valid user code in flash, USART, SPI, and I2C.
• Legacy, Single, and Dual image boot.
• OTP API for programming OTP memory.
• Random Number Generator (RNG) API.
LPC546xx
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© NXP Semiconductors N.V. 2018. All rights reserved.
Product data sheet
Rev. 2.5 — 20 June 2018
56 of 169
NXP [ NXP ]
