LPC546xx
NXP Semiconductors
32-bit ARM Cortex-M4 microcontroller
7.12.5 Clock Generation
to CPU, AHB bus,
00
10
11
Sync APB
CPU CLOCK
DIVIDER
pll_clk
32k_clk
fro_12m
clk_in
wdt_clk
fro_hf
(1)
00
01
10
11
main_clk
to EMC
EMC ClOCK
DIVIDER
AHBCLKDIV
(function
clock)
Main clock select B
MAINCLKSELB[1:0]
(1)
fro_hf
pll_clk
usb_pll_clk
audio_pll_clk
“none”
000
001
010
011
111
EMCCLKDIV
to ADC
ADC CLOCK
DIVIDER
Main clock select A
MAINCLKSELA[1:0]
fro_12m
clk_in
000
001
ADCCLKDIV
ADC clock select
ADCCLKSEL[2:0]
32k_clk
“none”
pll_clk
SYSTEM PLL
011
111
fro_hf
System PLL
settings
000
001
010
111
to USB0
(FS USB)
PLL clock select
SYSPLLCLKSEL[2:0]
pll_clk
usb_pll_clk
“none”
USB0 CLOCK
DIVIDER
xtalin
xtalout
USB0CLKDIV
clk_in
Crystal
oscillator
USB0 clock select
USB0CLKSEL[2:0]
Range select
SYSOSCCTRL[1:0]
main_clk
000
001
010
111
pll_clk
usb_pll_clk
“none”
to USB1 PHY
USB1 CLOCK
DIVIDER
fro_hf
fro_hf_div
FRO Clock
Divider
USB1CLKDIV
USB1 clock select
USB1CLKSEL[2:0]
FROHFCLKDIV
USB PLL
usb_pll_clk
clk_in
fro_12
to DMIC
subsystem
000
001
010
011
111
fro_hf_div
DMIC CLOCK
DIVIDER
audio_pll_clk
USB PLL
settings
mclk_in
“none”
DMICCLKDIV
fro_12m
clk_in
000
001
DMIC clock select
DMICCLKSEL[2:0]
audio_pll_clk
Audio PLL
“none”
111
fro_hf_div
to MCLK pin
(output)
000
001
AUDIO PLL Settings
audio_pll_clk
“none”
Audio clock select
AUDPLLCKSEL[2:0]
MCLK
DIVIDER
111
MCLKDIV
main_clk
MCLK clock select
MCLKCLKSEL[1:0]
00
fro_12m
01
audio_pll_clk
10
to Async APB
(1)
fc6_fclk
11
main_clk
pll_clk
usb_pll_clk
fro_hf
000
001
010
011
100
to SDIO
(function clock)
SDIO CLOCK
DIVIDER
APB clock select B
ASYNCAPBCLKSELA[1:0]
audio_pll_clk
SDIOCLKDIV
“none”
111
(1): synchronized multiplexer,
see register descriptions for details.
SDIO clock select
SDIOCLKSEL[2:0]
aaa-023922
Fig 11. LPC546xx clock generation
LPC546xx
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© NXP Semiconductors N.V. 2018. All rights reserved.
Product data sheet
Rev. 2.5 — 20 June 2018
62 of 169
NXP [ NXP ]
