LPC546xx
NXP Semiconductors
32-bit ARM Cortex-M4 microcontroller
7.10 EEPROM
The LPC546xx contains up to 16 kB byte of on-chip word-erasable and
word-programmable EEPROM data memory. EEPROM is not accessible in deep-sleep
and deep-power-down modes.
7.11 Memory mapping
The LPC546xx incorporates several distinct memory regions. The APB peripheral area is
512 kB in size and is divided to allow for up to 32 peripherals.Each peripheral is allocated
4 kB of space simplifying the address decoding. The registers incorporated into the CPU,
such as NVIC, SysTick, and sleep mode control, are located on the private peripheral bus.
The ARM Cortex-M4 processor has a single 4 GB address space. The following table
shows how this space is used on the LPC546xx.
Table 7.
Memory usage and details
Address range
0x0000 0000 to 0x1FFF FFFF On-chip
non-volatile
General Use
Address range details and description
0x0000 0000 - 0x0007 FFFF Flash memory (512 kB).
memory
Boot ROM
0x0300 0000 - 0x0300 FFFF Boot ROM with flash services in a 64 kB
space.
SRAMX
0x0400 0000 - 0x0400 7FFF I&D SRAM bank (32 kB).
SPI Flash
Interface (SPIFI)
0x1000 0000 - 0x17FF FFFF SPIFI memory mapped access space
(128 MB).
0x2000 0000 to 0x3FFF FFFF SRAM Banks
0x2000 0000 - 0x2002 7FFF SRAM banks (160 kB).
SRAM bit band 0x2200 0000 - 0x23FF FFFF SRAM bit band alias addressing (32
alias addressing MB)
0x4000 0000 to 0x7FFF FFFF APB peripherals 0x4000 0000 - 0x4001 FFFF APB slave group 0 up to 32 peripheral
blocks of 4 kB each (128 kB).
0x4002 0000 - 0x4003 FFFF APB slave group 1 up to 32 peripheral
blocks of 4 kB each (128 kB).
0x4004 0000 - 0x4005 FFFF APB asynchronous slave group 2 up to
32 peripheral blocks of 4 kB each
(128 kB).
AHB peripherals 0x4008 0000 - 0x400B FFFF AHB peripherals (256 kB).
Peripheral bit
band alias
0x4200 0000 - 0x43FF FFFF Peripheral bit band alias addressing
(32 MB)
addressing
LPC546xx
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© NXP Semiconductors N.V. 2018. All rights reserved.
Product data sheet
Rev. 2.5 — 20 June 2018
57 of 169
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