LPC540xx
NXP Semiconductors
32-bit ARM Cortex-M4 microcontroller
7.10.6 Brownout detection
The LPC540xx includes a monitor for the voltage level on the VDD pin. If this voltage falls
below a fixed level, the BOD sets a flag that can be polled or cause an interrupt. In
addition, a separate threshold level can be selected to cause chip reset.
7.10.7 Safety
The LPC540xx includes a Windowed WatchDog Timer (WWDT), which can be enabled by
software after reset. Once enabled, the WWDT remains locked and cannot be modified in
any way until a reset occurs.
7.11 Power control
The LPC540xx support a variety of power control features. In Active mode, when the chip
is running, power and clocks to selected peripherals can be adjusted for power
consumption. In addition, there are three special modes of processor power reduction with
different peripherals running: sleep mode, deep-sleep mode, and deep power-down mode
that can be activated using the power API library from the SDK software package.
7.11.1 Sleep mode
In sleep mode, the system clock to the CPU is stopped and execution of instructions is
suspended until either a reset or an interrupt occurs. Peripheral functions, if selected to be
clocked can continue operation during Sleep mode and may generate interrupts to cause
the processor to resume execution. Sleep mode eliminates dynamic power used by the
processor itself, memory systems and related controllers, internal buses, and unused
peripherals. The processor state and registers, peripheral registers, and internal SRAM
values are maintained, and the logic levels of the pins remain static.
7.11.2 Deep-sleep mode
In deep-sleep mode, the system clock to the processor is disabled as in sleep mode. All
analog blocks are powered down by default but can be selected to keep running through
the power API if needed as wake-up sources. The main clock and all peripheral clocks are
disabled. The FRO is disabled.
Deep-sleep mode eliminates all power used by analog peripherals and all dynamic power
used by the processor itself, memory systems and related controllers, and internal buses.
The processor state and registers, peripheral registers, and internal SRAM values are
maintained, and the logic levels of the pins remain static.
GPIO Pin Interrupts, GPIO Group Interrupts, and selected peripherals such as USB0,
USB1, DMIC, SPI, I2C, USART, WWDT, RTC, Micro-tick Timer, and BOD can be left
running in deep sleep mode The FRO, RTC oscillator, and the watchdog oscillator can be
left running.In some cases, DMA can operate in deep-sleep mode.
7.11.3 Deep power-down mode
In deep power-down mode, power is shut off to the entire chip except for the RTC power
domain and the RESET pin. The LPC540xx can wake up from deep power-down mode
via the RESET pin and the RTC alarm. The ALARM1HZ flag in RTC control register
generates an RTC wake-up interrupt request, which can wake up the part. During deep
power-down mode, the contents of the SRAM and registers are not retained. All functional
pins are tri-stated in deep power-down mode.
LPC540xx
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© NXP Semiconductors N.V. 2018. All rights reserved.
Product data sheet
Rev. 1.8 — 22 June 2018
65 of 168
NXP [ NXP ]
