LPC540xx
NXP Semiconductors
32-bit ARM Cortex-M4 microcontroller
Table 9.
Wake-up sources for reduced power modes
Power mode Wake-up source
Conditions
Deep
power-down
RTC 1 Hz alarm timer
• Enable the RTC 1 Hz oscillator in the RTC CTRL register.
• Start RTC alarm timer by writing a time-out value to the RTC COUNT register.
RTC 1 kHz timer
time-out and alarm
• Enable the RTC 1 Hz oscillator and the RTC 1 kHz oscillator in the RTCOSCC-
TRL register.
• Enable the RTC bus clock in the AHBCLKCTRL0 register.
• Start RTC 1 kHz timer by writing a value to the WAKE register of the RTC.
Always available.
Reset pin
7.12 General Purpose I/O (GPIO)
The LPC540xx provides six GPIO ports with a total of up to 171 GPIO pins.
Device pins that are not connected to a specific peripheral function are controlled by the
GPIO registers. Pins may be dynamically configured as inputs or outputs. Separate
registers allow setting or clearing any number of outputs simultaneously. The current level
of a port pin can be read back no matter what peripheral is selected for that pin.
7.12.1 Features
• Accelerated GPIO functions:
– GPIO registers are located on the AHB so that the fastest possible I/O timing can
be achieved.
– Mask registers allow treating sets of port bits as a group, leaving other bits
unchanged.
– All GPIO registers are byte and half-word addressable.
– Entire port value can be written in one instruction.
• Bit-level set and clear registers allow a single instruction set or clear of any number of
bits in one port.
• Direction control of individual bits.
• All I/O default to inputs after reset.
• All GPIO pins can be selected to create an edge or level-sensitive GPIO interrupt
request.
• One GPIO group interrupt can be triggered by a combination of any pin or pins.
7.13 Pin interrupt/pattern engine
The pin interrupt block configures up to eight pins from all digital pins for providing eight
external interrupts connected to the NVIC. The pattern match engine can be used in
conjunction with software to create complex state machines based on pin inputs. Any
digital pin, independent of the function selected through the switch matrix can be
configured through the SYSCON block as an input to the pin interrupt or pattern match
engine. The registers that control the pin interrupt or pattern match engine are located on
the I/O+ bus for fast single-cycle access.
LPC540xx
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© NXP Semiconductors N.V. 2018. All rights reserved.
Product data sheet
Rev. 1.8 — 22 June 2018
68 of 168
NXP [ NXP ]
