LPC540xx
NXP Semiconductors
32-bit ARM Cortex-M4 microcontroller
7.10.5 Clock Generation
00
01
10
to CPU, AHB bus,
“none”
Sync APB
CPU CLOCK
DIVIDER
pll_clk
fro_12m
00
32k_clk
(1)
main_clk
11
clk_in
01
to EMC
(function
clock)
EMC ClOCK
DIVIDER
AHBCLKDIV
wdt_clk
10
Main clock select B
MAINCLKSELB[1:0]
fro_hf
11
(1)
fro_hf
pll_clk
usb_pll_clk
audio_pll_clk
“none”
EMCCLKDIV
000
001
010
011
111
Main clock select A
MAINCLKSELA[1:0]
to ADC
ADC CLOCK
DIVIDER
fro_12m
clk_in
000
001
ADCCLKDIV
ADC clock select
ADCCLKSEL[2:0]
32k_clk
“none”
pll_clk
SYSTEM PLL
011
111
fro_hf
System PLL
settings
000
001
010
111
to USB0
(FS USB)
PLL clock select
SYSPLLCLKSEL[2:0]
pll_clk
usb_pll_clk
“none”
USB0 CLOCK
DIVIDER
xtalin
xtalout
USB0CLKDIV
clk_in
Crystal
oscillator
USB0 clock select
USB0CLKSEL[2:0]
Range select
SYSOSCCTRL[1:0]
main_clk
000
001
010
111
pll_clk
usb_pll_clk
“none”
to USB1 PHY
USB1 CLOCK
DIVIDER
fro_hf
fro_hf_div
FRO Clock
Divider
USB1CLKDIV
USB1 clock select
USB1CLKSEL[2:0]
FROHFCLKDIV
USB PLL
usb_pll_clk
clk_in
fro_12
to DMIC
000
001
010
011
100
101
fro_hf_div
audio_pll_clk
mclk_in
subsystem
DMIC CLOCK
DIVIDER
USB PLL
settings
main_clk
wdt_in
DMICCLKDIV
fro_12m
clk_in
000
001
111
“none”
audio_pll_clk
111
Audio PLL
“none”
DMIC clock select
DMICCLKSEL[2:0]
AUDIO PLL Settings
Audio clock select
AUDPLLCKSEL[2:0]
fro_hf_div
to MCLK pin
(output)
000
001
audio_pll_clk
“none”
MCLK
DIVIDER
main_clk
111
00
fro_12m
01
audio_pll_clk
10
to Async APB
MCLKDIV
MCLK clock select
MCLKCLKSEL[1:0]
fc6_fclk
(1)
11
main_clk
000
001
010
011
100
APB clock select B
ASYNCAPBCLKSELA[1:0]
pll_clk
usb_pll_clk
fro_hf
to SDIO
(function clock)
SDIO CLOCK
DIVIDER
audio_pll_clk
SDIOCLKDIV
“none”
111
(1): synchronized multiplexer,
see register descriptions for details.
SDIO clock select
SDIOCLKSEL[2:0]
aaa-029067
Fig 11. LPC540xx clock generation
LPC540xx
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© NXP Semiconductors N.V. 2018. All rights reserved.
Product data sheet
Rev. 1.8 — 22 June 2018
63 of 168
NXP [ NXP ]
