LPC540xx
NXP Semiconductors
32-bit ARM Cortex-M4 microcontroller
7.13.1 Features
• Pin interrupts:
– Up to eight pins can be selected from all GPIO pins on ports 0 and 1 as
edge-sensitive or level-sensitive interrupt requests. Each request creates a
separate interrupt in the NVIC.
– Edge-sensitive interrupt pins can interrupt on rising or falling edges or both.
– Level-sensitive interrupt pins can be HIGH-active or LOW-active.
– Level-sensitive interrupt pins can be HIGH-active or LOW-active.
– Pin interrupts can wake up the device from sleep mode and deep-sleep mode.
• Pattern match engine:
– Up to eight pins can be selected from all digital pins on ports 0 and 1 to contribute
to a boolean expression. The boolean expression consists of specified levels
and/or transitions on various combinations of these pins.
– Each bit slice minterm (product term) comprising of the specified boolean
expression can generate its own, dedicated interrupt request.
– Any occurrence of a pattern match can also be programmed to generate an RXEV
notification to the CPU. The RXEV signal can be connected to a pin.
– Pattern match can be used in conjunction with software to create complex state
machines based on pin inputs.
– Pattern match engine facilities wake-up only from active and sleep modes.
7.14 Serial peripherals
7.14.1 Full-speed USB Host/Device interface (USB0)
The Universal Serial Bus (USB) is a 4-wire bus that supports communication between a
host and one or more (up to 127) peripherals. The host controller allocates the USB
bandwidth to attached devices through a token-based protocol. The bus supports hot
plugging and dynamic configuration of the devices. All transactions are initiated by the
host controller.
7.14.1.1 USB0 device controller
The device controller enables 12 Mbit/s data exchange with a USB host controller. It
consists of a register interface, serial interface engine, endpoint buffer memory. The serial
interface engine decodes the USB data stream and writes data to the appropriate
endpoint buffer. The status of a completed USB transfer or error condition is indicated via
status registers. An interrupt is also generated if enabled.
Features
• Supports 10 physical (5 logical) endpoints including two control endpoints.
• Single and double-buffering supported.
• Each non-control endpoint supports bulk, interrupt, or isochronous endpoint types.
• Supports wake-up from reduced power mode on USB activity and remote wake-up.
• Supports SoftConnect.
• Link Power Management (LPM) supported.
LPC540xx
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2018. All rights reserved.
Product data sheet
Rev. 1.8 — 22 June 2018
69 of 168
NXP [ NXP ]
