LPC540xx
NXP Semiconductors
32-bit ARM Cortex-M4 microcontroller
Table 48. Dynamic characteristics: Ethernet
Tamb = 40 C to 105 C, VDD = 2.7 V to 3.6 V. CL = 30 pF balanced loading on all pins; Input slew = 1 ns, SLEW setting =
standard mode for all pins; Parameters sampled at the 90 % and 10 % level of the rising or falling edge. Based on simulation.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
[1][2]
th
data input hold time for ENET_RXDn, ENET_RX_ER,
ENET_RX_DV
CCLK 100 MHz
1.2
1.2
-
-
0
0
ns
ns
CCLK > 100 MHz
[1][2]
tv(Q)
data output valid
time
for ENET_TXDn, ENET_TX_EN,
ENET_TX_ER
CCLK 100 MHz
10.0
10.0
-
-
18.2
18.2
ns
ns
CCLK > 100 MHz
[1] Output drivers can drive a load 25 pF accommodating over 12 inch of PCB trace and the input
capacitance of the receiving device.
[2] Timing values are given from the point at which the clock signal waveform crosses 1.4 V to the valid input or
output level.
ENET_RX_CLK
t
v(Q)
ENET_TX_EN
ENET_TXDn
t
su
t
h
ENET_RXDn
ENET_RX_DV
aaa-025108
Fig 38. Ethernet RMII timing
ENET_RX_CLK
t
su
t
h
ENET_RXDn
ENET_RX_DV
ENET_RX_ER
ENET_TX_CLK
t
v(Q)
ENET_TX_EN
ENET_TXDn
aaa-025109
Fig 39. Ethernet MII timing
LPC540xx
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© NXP Semiconductors N.V. 2018. All rights reserved.
Product data sheet
Rev. 1.8 — 22 June 2018
134 of 168
NXP [ NXP ]
