LPC540xx
NXP Semiconductors
32-bit ARM Cortex-M4 microcontroller
11.23 SD/MMC and SDIO
Table 49. Dynamic characteristics: SD/MMC and SDIO
amb = 40 C to +105 C, VDD = 2.7 V to 3.6 V; CL = 20 pF. SAMPLE_DELAY = 0, DRV_DELAY = 0 in the SDDELAY
T
register, SDIOCLKCTRL = 0x84, sampled at 90 % and 10 % of the signal level, SLEW = 1 ns for SD_CLK pin, SLEW = 1 ns
for SD_DATn and SD_CMD pins. Simulated values in high-speed mode.
Symbol
fclk
Parameter
Conditions
Min
Typ
Max
Unit
clock frequency
data input set-up time
on pin SD_CLK; data transfer mode
on pins SD_DATn as inputs
CCLK 100 MHz
-
-
50
MHz
tsu(D)
14.4
14.4
-
-
-
-
ns
ns
CCLK > 100 MHz
on pins SD_CMD as inputs
CCLK 100 MHz
14.4
14.4
-
-
-
-
ns
ns
CCLK > 100 MHz
th(D)
data input hold time
on pins SD_DATn as inputs
CCLK 100 MHz
1.5
1.5
-
-
-
-
ns
ns
CCLK > 100 MHz
on pins SD_CMD as inputs
CCLK 100 MHz
1.5
1.5
-
-
-
-
ns
ns
CCLK > 100 MHz
tv(Q)
data output valid time
on pins SD_DATn as outputs
CCLK 100 MHz
1.9
1.9
-
-
3.5
3.5
ns
ns
CCLK > 100 MHz
on pins SD_CMD as outputs
CCLK 100 MHz
1.9
1.9
-
-
3.5
3.5
ns
ns
CCLK > 100 MHz
T
cy(clk)
SD_CLK
t
t
d(QV)
h(Q)
SD_CMD (O)
SD_DATn (O)
t
t
su(D)
h(D)
SD_CMD (I)
SD_DATn (I)
002aag204
Fig 40. SD/MMC and SDIO timing
LPC540xx
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© NXP Semiconductors N.V. 2018. All rights reserved.
Product data sheet
Rev. 1.8 — 22 June 2018
135 of 168
NXP [ NXP ]
