LPC540xx
NXP Semiconductors
32-bit ARM Cortex-M4 microcontroller
T
cy(clk)
Un_SCLK (CLKPOL = 0)
Un_SCLK (CLKPOL = 1)
TXD
t
t
vQ)
v(Q)
START
BIT0
BIT1
t
t
su(D) h(D)
BIT1
START
BIT0
RXD
aaa-015074
Fig 36. USART timing
11.19 SCTimer/PWM output timing
Table 46. SCTimer/PWM output dynamic characteristics
Tamb = 40 C to 105 C; 1.71 V VDD 3.6 V CL = 30 pF. Simulated skew (over process, voltage, and temperature) of any
two SCT fixed-pin output signals; sampled at the 90 % and 10 % level of the rising or falling edge; values guaranteed by
design.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tsk(o)
output skew time
-
3.4
-
4.5
ns
11.20 USB interface characteristics
Table 47. Dynamic characteristics: USB0 pins (full-speed)
CL = 50 pF; Rpu = 1.5 k on D+ to VDD, unless otherwise specified; 3.0 V VDD 3.6 V.
Symbol
tr
Parameter
rise time
fall time
Conditions
10 % to 90 %
10 % to 90 %
Min
4.0
4.0
90
Typ
Max
20
Unit
ns
ns
%
tf
20
tFRFM
VCRS
tFEOPT
tFDEOP
differential rise and fall time matching tr / tf
output signal crossover voltage
111.11
2.0
1.3
160
2
V
source SE0 interval of EOP
see Figure 37
175
+5
ns
ns
source jitter for differential transition see Figure 37
to SE0 transition
tJR1
receiver jitter to next transition
18.5
9
+18.5
+9
ns
ns
ns
tJR2
receiver jitter for paired transitions
EOP width at receiver
10 % to 90 %
-
-
[1]
[1]
tEOPR1
must reject as
EOP; see
Figure 37
40
tEOPR2
EOP width at receiver
must accept as
EOP; see
82
-
-
ns
Figure 37
[1] Characterized but not implemented as production test. Guaranteed by design.
LPC540xx
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2018. All rights reserved.
Product data sheet
Rev. 1.8 — 22 June 2018
132 of 168
NXP [ NXP ]
