LPC540xx
NXP Semiconductors
32-bit ARM Cortex-M4 microcontroller
11.21
T
PERIOD
crossover point
extended
crossover point
differential
data lines
source EOP width: t
FEOPT
differential data to
SE0/EOP skew
n × T
+ t
PERIOD
FDEOP
receiver EOP width: t
, t
EOPR1 EOPR2
002aab561
Fig 37. Differential data-to-EOP transition skew and EOP width
11.22 Ethernet AVB
Remark: The timing characteristics of the ENET_MDC and ENET_MDIO signals comply
with the IEEE standard 802.3.
Table 48. Dynamic characteristics: Ethernet
Tamb = 40 C to 105 C, VDD = 2.7 V to 3.6 V. CL = 30 pF balanced loading on all pins; Input slew = 1 ns, SLEW setting =
standard mode for all pins; Parameters sampled at the 90 % and 10 % level of the rising or falling edge. Based on simulation.
Symbol
RMII mode
fclk
Parameter
Conditions
Min
Typ
Max
Unit
[1]
clock frequency
clock duty cycle
for ENET_RX_CLK
-
-
-
50.0
55.0
MHz
%
[1]
clk
45.0
[1][2]
tsu
data input set-up
time
ENET_RXDn, ENET_RX_ER,
ENET_RX_DV
CCLK 100 MHz
4.4
4.4
-
-
-
-
ns
ns
CCLK > 100 MHz
[1][2]
[1][2]
th
data input hold time for ENET_RXDn, ENET_RX_ER,
ENET_RX_DV
CCLK 100 MHz
1.3
1.3
-
-
0
0
ns
ns
CCLK > 100 MHz
tv(Q)
data output valid
time
for ENET_TXDn, ENET_TX_EN
CCLK 100 MHz
9.9
9.9
-
-
17.3
17.3
ns
ns
CCLK > 100 MHz
MII mode
[1]
fclk
clk
fclk
clk
tsu
clock frequency
clock duty cycle
clock frequency
clock duty cycle
for ENET_TX_CLK
for ENET_RX_CLK
-
-
-
-
-
25.0
55.0
25.0
55.0
MHz
%
[1]
45.0
-
[1]
MHz
%
[1]
45.0
[1][2]
data input set-up
time
for ENET_RXDn, ENET_RX_ER,
ENET_RX_DV
CCLK 100 MHz
4.7
4.7
-
-
-
-
ns
ns
CCLK > 100 MHz
LPC540xx
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© NXP Semiconductors N.V. 2018. All rights reserved.
Product data sheet
Rev. 1.8 — 22 June 2018
133 of 168
NXP [ NXP ]
