LPC2210/2220
NXP Semiconductors
16/32-bit ARM microcontrollers
Table 4.
Pin description …continued
Symbol
Pin (LQFP)
46[5]
45[5]
44[5]
41[5]
Pin (TFBGA) Type
Description
P3.19/A19
P3.20/A20
P3.21/A21
P3.22/A22
L5[5]
K5[5]
N4[5]
K4[5]
N3[5]
O
O
O
O
O
O
O
A19 — External memory address line 19.
A20 — External memory address line 20.
A21 — External memory address line 21.
A22 — External memory address line 22.
A23 — External memory address line 23.
XCLK — Clock output.
P3.23/A23/
XCLK
40[5]
P3.24/CS3
P3.25/CS2
P3.26/CS1
P3.27/WE
36[5]
35[5]
30[5]
M2[5]
M1[5]
K2[5]
CS3 — LOW-active Chip Select 3 signal.
(Bank 3 addresses range 0x8300 0000 to 0x83FF FFFF)
CS2 — LOW-active Chip Select 2 signal.
(Bank 2 addresses range 0x8200 0000 to 0x82FF FFFF)
CS1 — LOW-active Chip Select 1 signal.
(Bank 1 addresses range 0x8100 0000 to 0x81FF FFFF)
WE — LOW-active Write enable signal.
O
O
29[5]
28[2]
K1[5]
J4[2]
O
O
I
P3.28/BLS3/
AIN7
BLS3 — LOW-active Byte Lane Select signal (Bank 3).
AIN7 — ADC, input 7. This analog input is always connected
to its pin.
P3.29/BLS2/
AIN6
27[4]
J3[4]
O
I
BLS2 — LOW-active Byte Lane Select signal (Bank 2).
AIN6 — ADC, input 6. This analog input is always connected
to its pin.
P3.30/BLS1
P3.31/BLS0
n.c.
97[4]
96[4]
22[5]
E13[4]
F10[4]
H2[5]
O
O
BLS1 — LOW-active Byte Lane Select signal (Bank 1).
BLS0 — LOW-active Byte Lane Select signal (Bank 0).
Not connected. This pin MUST NOT be pulled LOW or the
device might not operate properly.
RESET
135[6]
C5[6]
I
External reset input: A LOW on this pin resets the device,
causing I/O ports and peripherals to take on their default
states, and processor execution to begin at address 0. TTL
with hysteresis, 5 V tolerant.
XTAL1
142[7]
141[7]
C3[7]
B3[7]
I
Input to the oscillator circuit and internal clock generator
circuits.
XTAL2
VSS
O
I
Output from the oscillator amplifier.
3, 9, 26, 38, C2, E4, J2,
54, 67, 79, N2, N7, L10,
93, 103, 107, K12, F13,
Ground: 0 V reference.
111, 128
D11, B13,
B11, D7
VSSA
139
C4
I
I
I
Analog ground: 0 V reference. This should nominally be the
same voltage as VSS, but should be isolated to minimize noise
and error.
VSSA(PLL)
138
B4
PLL analog ground: 0 V reference. This should nominally be
the same voltage as VSS, but should be isolated to minimize
noise and error.
VDD(1V8)
37, 110
N1, A12
1.8 V core power supply: This is the power supply voltage
for internal circuitry.
LPC2210_2220_6
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 06 — 11 December 2008
13 of 50
NXP [ NXP ]
