LPC2210/2220
NXP Semiconductors
16/32-bit ARM microcontrollers
4.0 GB
3.75 GB
3.5 GB
0xFFFF FFFF
AHB PERIPHERALS
APB PERIPHERALS
0xF000 0000
0xEFFF FFFF
0xE000 0000
0xDFFF FFFF
RESERVED ADDRESS SPACE
3.0 GB
0x8400 0000
0x83FF FFFF
EXTERNAL MEMORY BANK 3
EXTERNAL MEMORY BANK 2
EXTERNAL MEMORY BANK 1
EXTERNAL MEMORY BANK 0
0x8300 0000
0x82FF FFFF
0x8200 0000
0x81FF FFFF
0x8100 0000
0x80FF FFFF
0x8000 0000
0x7FFF FFFF
2.0 GB
BOOT BLOCK (RE-MAPPED FROM
ON-CHIP ROM MEMORY)
0x7FFF E000
0x7FFF DFFF
RESERVED ADDRESS SPACE
0x4001 0000
0x4000 FFFF
64 kB ON-CHIP STATIC RAM (LPC2220)
16 kB ON-CHIP STATIC RAM (LPC2210)
0x4000 4000
0x4000 3FFF
0x4000 0000
0x3FFF FFFF
1.0 GB
RESERVED ADDRESS SPACE
0x0000 0000
002aaa795
0.0 GB
Fig 4. LPC2210/2220 memory map
6.4 Interrupt controller
The VIC accepts all of the interrupt request inputs and categorizes them as Fast Interrupt
Request (FIQ), vectored Interrupt Request (IRQ), and non-vectored IRQ as defined by
programmable settings. The programmable assignment scheme means that priorities of
interrupts from the various peripherals can be dynamically assigned and adjusted.
FIQ has the highest priority. If more than one request is assigned to FIQ, the VIC
combines the requests to produce the FIQ signal to the ARM processor. The fastest
possible FIQ latency is achieved when only one request is classified as FIQ, because then
the FIQ service routine can simply start dealing with that device. But if more than one
request is assigned to the FIQ class, the FIQ service routine can read a word from the VIC
that identifies which FIQ source(s) is (are) requesting an interrupt.
Vectored IRQs have the middle priority. Sixteen of the interrupt requests can be assigned
to this category. Any of the interrupt requests can be assigned to any of the 16 vectored
IRQ slots, among which slot 0 has the highest priority and slot 15 has the lowest.
LPC2210_2220_6
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 06 — 11 December 2008
16 of 50
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