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LPC2220FBD144-S 参数 Datasheet PDF下载

LPC2220FBD144-S图片预览
型号: LPC2220FBD144-S
PDF下载: 下载PDF文件 查看货源
内容描述: [16/32-bit ARM microcontrollers; flashless, with 10-bit ADC and external memory interface - ADCs: 8-ch 10-bit ; Category: ARM7TDMI-S (TM) Core ; Clock type: N/A ; External interrupt: 3 ; Function: 16/32-bit uController ; I/O pins: 112 ; Memory size: - kBits; Memory type: ROMless ; Number of pins: 144 ; Operating frequency: 0~75 MHz; Operating temperature: -40 to +85 Cel; Power supply: 1.8V (CPU)3.3V (I/O) ; PWMs: 6-ch PWM ; RAM: 64KB bytes; Reset active: Low ; Serial interface: 2xUARTI2C1xSPI 1xS]
分类和应用: 存储微控制器
文件页数/大小: 50 页 / 259 K
品牌: NXP [ NXP ]
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LPC2210/2220  
NXP Semiconductors  
16/32-bit ARM microcontrollers  
Table 4.  
Symbol  
Pin description …continued  
Pin (LQFP)  
Pin (TFBGA) Type  
Description  
P0.13/DTR1/  
MAT1.1  
85[1]  
H10[1]  
O
O
I
DTR1 — Data Terminal Ready output for UART1.  
MAT1.1 — Match output for Timer 1, channel 1.  
DCD1 — Data Carrier Detect input for UART1.  
EINT1 — External interrupt 1 input.  
P0.14/DCD1/  
EINT1  
92[2]  
G10[2]  
I
Note: LOW on this pin while RESET is LOW forces on-chip  
bootloader to take over control of the part after reset.  
P0.15/RI1/  
EINT2  
99[2]  
E11[2]  
E10[2]  
I
RI1 — Ring Indicator input for UART1.  
I
EINT2 — External interrupt 2 input.  
P0.16/EINT0/  
100[2]  
I
EINT0 — External interrupt 0 input.  
MAT0.2/CAP0.2  
O
MAT0.2 — Match output for Timer 0, channel 2.  
CAP0.2 — Capture input for Timer 0, channel 2.  
CAP1.2 — Capture input for Timer 1, channel 2.  
I
P0.17/CAP1.2/ 101[1]  
SCK1/MAT1.2  
D13[1]  
D8[1]  
C8[1]  
I
I/O  
SCK1 — Serial Clock for SPI1/SSI/Microwire.  
SPI/SSI/Microwire clock output from master or input to slave.  
O
I
MAT1.2 — Match output for Timer 1, channel 2.  
CAP1.3 — Capture input for Timer 1, channel 3.  
P0.18/CAP1.3/ 121[1]  
MISO1/MAT1.3  
I/O  
MISO1 — Master In Slave Out for SPI1. Data input to SPI  
master or data output from SPI slave.  
O
MAT1.3 — Match output for Timer 1, channel 3.  
MAT1.2 — Match output for Timer 1, channel 2.  
P0.19/MAT1.2/ 122[1]  
MOSI1/CAP1.2  
O
I/O  
MOSI1 — Master Out Slave In for SPI1. Data output from SPI  
master or data input to SPI slave.  
SPI interface: MOSI line.  
SSI: DX/RX line (SPI1 as a master/slave).  
Microwire: SO/SI line (SPI1 as a master/slave).  
CAP1.2 — Capture input for Timer 1, channel 2.  
MAT1.3 — Match output for Timer 1, channel 3.  
I
P0.20/MAT1.3/ 123[2]  
SSEL1/ EINT3  
B8[2]  
O
I
SSEL1 — Slave Select for SPI1/Microwire. Used to select the  
SPI or Microwire interface as a slave. Frame synchronization  
in case of 4-wire SSI.  
I
EINT3 — External interrupt 3 input.  
P0.21/PWM5/  
CAP1.3  
4[1]  
C1[1]  
D4[1]  
O
I
PWM5 — Pulse Width Modulator output 5.  
CAP1.3 — Capture input for Timer 1, channel 3.  
CAP0.0 — Capture input for Timer 0, channel 0.  
MAT0.0 — Match output for Timer 0, channel 0.  
General purpose bidirectional digital port only.  
General purpose bidirectional digital port only.  
General purpose bidirectional digital port only.  
P0.22/CAP0.0/ 5[1]  
MAT0.0  
I
O
I/O  
I/O  
I/O  
I
P0.23  
P0.24  
P0.25  
6[1]  
8[1]  
21[1]  
23[4]  
D3[1]  
D1[1]  
H1[1]  
H3[4]  
P0.27/AIN0/  
AIN0 — ADC, input 0. This analog input is always connected  
CAP0.1/MAT0.1  
to its pin.  
I
CAP0.1 — Capture input for Timer 0, channel 1.  
MAT0.1 — Match output for Timer 0, channel 1.  
O
LPC2210_2220_6  
© NXP B.V. 2008. All rights reserved.  
Product data sheet  
Rev. 06 — 11 December 2008  
9 of 50  
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