LPC2210/2220
NXP Semiconductors
16/32-bit ARM microcontrollers
Non-vectored IRQs have the lowest priority.
The VIC combines the requests from all the vectored and non-vectored IRQs to produce
the IRQ signal to the ARM processor. The IRQ service routine can start by reading a
register from the VIC and jumping there. If any of the vectored IRQs are requesting, the
VIC provides the address of the highest-priority requesting IRQs service routine,
otherwise it provides the address of a default routine that is shared by all the non-vectored
IRQs. The default routine can read another VIC register to see what IRQs are active.
6.4.1 Interrupt sources
Table 5 lists the interrupt sources for each peripheral function. Each peripheral device has
one interrupt line connected to the VIC, but may have several internal interrupt flags.
Individual interrupt flags may also represent more than one interrupt source.
Table 5.
Block
Interrupt sources
Flag(s)
VIC channel #
WDT
Watchdog Interrupt (WDINT)
0
1
2
3
4
5
6
-
Reserved for software interrupts only
EmbeddedICE, DbgCommRX
EmbeddedICE, DbgCommTX
Match 0 to 3 (MR0, MR1, MR2, MR3)
Match 0 to 3 (MR0, MR1, MR2, MR3)
RX Line Status (RLS)
ARM Core
ARM Core
TIMER0
TIMER1
UART0
Transmit Holding Register Empty (THRE)
RX Data Available (RDA)
Character Time-out Indicator (CTI)
RX Line Status (RLS)
UART1
7
Transmit Holding Register empty (THRE)
RX Data Available (RDA)
Character Time-out Indicator (CTI)
Modem Status Interrupt (MSI)
Match 0 to 6 (MR0, MR1, MR2, MR3, MR4, MR5, MR6)
SI (state change)
PWM0
I2C
8
9
SPI0
SPIF, MODF
10
11
12
13
14
15
16
17
18
SPI1 and SSP
PLL
SPIF, MODF and TXRIS, RXRIS, RTRIS, RORRIS
PLL Lock (PLOCK)
RTC
RTCCIF (Counter Increment), RTCALF (Alarm)
System Control External Interrupt 0 (EINT0)
External Interrupt 1 (EINT1)
External Interrupt 2 (EINT2)
External Interrupt 3 (EINT3)
A/D
ADC
LPC2210_2220_6
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 06 — 11 December 2008
17 of 50
NXP [ NXP ]
