NXP Semiconductors
FXTH87E
FXTH87E, Family of Tire Pressure Monitor Sensors
11.4 Register definition
The TPM1 includes:
• An 8-bit status and control register (TPMSC)
• A 16-bit counter (TPMCNTH:TPMCNTL)
• A 16-bit modulo register (TPMMODH:TPMMODL)
Each timer channel has:
• An 8-bit status and control register (TPMCnSC)
• A 16-bit channel value register (TPMCnVH:TPMCnVL)
11.4.1 Timer status and control register (TPM1SC)
TPM1SC contains the overflow status flag and control bits that are used to configure the
interrupt enable, TPM1 configuration, clock source, and prescale divisor. These controls
relate to all channels within this timer module.
Table 79.ꢀTimer status and control register (TPM1SC) (address $0010)
Bit
R
7
6
TOIE
0
5
CPWMS
0
4
CLKSB
0
3
CLKSA
0
2
PS2
0
1
PS1
0
0
PS0
0
TOF
W
Reset
0
= Reserved
Table 80.ꢀ TPM1SC register field descriptions
Field
Description
Timer Overflow Flag — This flag is set when the TPM1 counter changes to 0x0000 after reaching the
modulo value programmed in the TPM1 counter modulo registers. When the TPM1 is configured for CPWM,
TOF is set after the counter has reached the value in the modulo register, at the transition to the next lower
count value. Clear TOF by reading the TPM1 status and control register when TOF is set and then writing a
0 to TOF. If another TPM1 overflow occurs before the clearing sequence is complete, the sequence is reset
so TOF would remain set after the clear sequence was completed for the earlier TOF. Reset clears TOF.
Writing a 1 to TOF has no effect.
7
TOF
0ꢀTPM1 counter has not reached modulo value or overflow
1ꢀTPM1 counter has overflowed
Timer Overflow Interrupt Enable — This read/write bit enables TPM1 overflow interrupts. If TOIE is set, an
interrupt is generated when TOF equals 1. Reset clears TOIE.
6
0ꢀTOF interrupts inhibited (use software polling)
1ꢀTOF interrupts enabled
TOIE
Center-Aligned PWM Select — This read/write bit selects CPWM operating mode. Reset clears this bit
so the TPM1 operates in up-counting mode for input capture, output compare, and edge-aligned PWM
functions. Setting CPWMS reconfigures the TPM1 to operate in up-/down-counting mode for CPWM
functions. Reset clears CPWMS.
5
CPWMS
0ꢀAll TPM channels operate as input capture, output compare, or edge-aligned PWM mode as selected by
the MSnB:MSnA control bits in each channel’s status and control register
1ꢀAll TPM channels operate in center-aligned PWM mode
FXTH87ERM
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Reference manual
Rev. 5.0 — 4 February 2019
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