NXP Semiconductors
FXTH87E
FXTH87E, Family of Tire Pressure Monitor Sensors
BACKGROUND mode became active even if one or both bytes of the counter are read
while BACKGROUND mode is active.
11.4.3 Timer counter modulo registers (TPM1MODH:TPM1MODL)
The read/write TPM1 modulo registers contain the modulo value for the TPM1 counter.
After the TPM1 counter reaches the modulo value, the TPM1 counter resumes counting
from 0x0000 at the next clock (CPWMS = 0) or starts counting down (CPWMS = 1), and
the overflow flag (TOF) becomes set. Writing to TPM1MODH or TPM1MODL inhibits
TOF and overflow interrupts until the other byte is written. Reset sets the TPM1 counter
modulo registers to 0x0000, which results in a free-running timer counter (modulo
disabled).
Table 84.ꢀTimer counter modulo register high (TPM1MODH) (address $0013)
Bit
R
7
Bit 15
0
6
14
0
5
13
0
4
12
0
3
11
0
2
10
0
1
9
0
0
Bit 8
0
W
Reset
Table 85.ꢀTimer counter modulo register low (TPM1MODL) (address $0014)
Bit
R
7
Bit 7
0
6
6
0
5
5
0
4
4
0
3
3
0
2
2
0
1
1
0
0
Bit 0
0
W
Reset
It is good practice to wait for an overflow interrupt so both bytes of the modulo register
can be written well before a new overflow. An alternative approach is to reset the TPM1
counter before writing to the TPM1 modulo registers to avoid confusion about when the
first counter overflow will occur.
11.4.4 Timer channel 0 status and control register (TPM1C0SC)
TPM1C0SC contains the channel interrupt status flag and control bits that are used to
configure the interrupt enable, channel configuration, and pin function.
Table 86.ꢀTimer channel 0 status and control register (TPM1C0SC) (address $0015)
Bit
R
7
CH0F
0
6
CH0IE
0
5
MS0B
0
4
MS0A
0
3
ELS0B
0
2
ELS0A
0
1
0
0
0
W
Reset
0
0
= Reserved
FXTH87ERM
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Reference manual
Rev. 5.0 — 4 February 2019
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