NXP Semiconductors
FXTH87E
FXTH87E, Family of Tire Pressure Monitor Sensors
Bit-Manipulation
Branch
Read-Modify-Write
Control
Register/Memory
05ꢁꢁ5 15ꢁꢁ5 25ꢁꢁ3 35ꢁꢁ4 45ꢁꢁ3 55ꢁꢁ4 65ꢁꢁ3 75ꢁꢁ5 85ꢁꢁ1 95ꢁꢁ2 A5ꢁꢁ2 B5ꢁꢁ3 C5ꢁꢁ4 D5ꢁꢁ4 E5ꢁꢁ3 F5ꢁꢁ3
BRCLR2
BCLR2
BCS
STHX
LDHX
LDHX
CPHX
CPHX
TPA
TSX
BIT
BIT
BIT
BIT
BIT
BIT
3ꢁꢁ
DIR
2ꢁꢁ
DIR
2ꢁꢁrel
2ꢁꢁ
DIR
3ꢁꢁ
IMM
2ꢁꢁ
DIR
3ꢁꢁ
IMM
2ꢁꢁ
DIR
1ꢁꢁ
INH
1ꢁꢁ
INH
2ꢁꢁ
IMM
2ꢁꢁ
DIR
3ꢁꢁ
EXT
3ꢁꢁIX2 2ꢁꢁIX1 1ꢁꢁIX
06ꢁꢁ5 16ꢁꢁ5 26ꢁꢁ3 36ꢁꢁ5 46ꢁꢁ1 56ꢁꢁ1 66ꢁꢁ5 76ꢁꢁ4 86ꢁꢁ3 96ꢁꢁ5 A6ꢁꢁ2 B6ꢁꢁ3 C6ꢁꢁ4 D6ꢁꢁ4 E6ꢁꢁ3 F6ꢁꢁ3
BRSET3
BSET3
BNE
ROR
RORA
RORX
ROR
ROR
PULA
STHX
LDA
LDA
LDA
LDA
LDA
LDA
3ꢁꢁ
DIR
2ꢁꢁ
DIR
2ꢁꢁrel
2ꢁꢁ
DIR
1ꢁꢁ
INH
1ꢁꢁ
INH
2ꢁꢁIX1 1ꢁꢁIX
1ꢁꢁ
INH
3ꢀEXT
2ꢁꢁ
IMM
2ꢁꢁ
DIR
3ꢁꢁ
EXT
3ꢁꢁIX2 2ꢁꢁIX1 1ꢁꢁIX
07ꢁꢁ5 17ꢁꢁ5 27ꢁꢁ3 37ꢁꢁ5 47ꢁꢁ1 57ꢁꢁ1 67ꢁꢁ5 77ꢁꢁ4 87ꢁꢁ2 97ꢁꢁ1 A7ꢁꢁ2 B7ꢁꢁ3 C7ꢁꢁ4 D7ꢁꢁ4 E7ꢁꢁ3 F7ꢁꢁ2
BRCLR3
BCLR3
BEQ
ASR
ASRA
ASRX
ASR
ASR
PSHA
TAX
AIS
STA
STA
STA
STA
STA
3ꢁꢁ
DIR
2ꢁꢁ
DIR
2ꢁꢁrel
2ꢁꢁ
DIR
1ꢁꢁ
INH
1ꢁꢁ
INH
2ꢁꢁIX1 1ꢁꢁIX
1ꢁꢁ
INH
1ꢁꢁ
INH
2ꢁꢁ
IMM
2ꢁꢁ
DIR
3ꢁꢁ
EXT
3ꢁꢁIX2 2ꢁꢁIX1 1ꢁꢁIX
08ꢁꢁ5 18ꢁꢁ5 28ꢁꢁ3 38ꢁꢁ5 48ꢁꢁ1 58ꢁꢁ1 68ꢁꢁ5 78ꢁꢁ4 88ꢁꢁ3 98ꢁꢁ1 A8ꢁꢁ2 B8ꢁꢁ3 C8ꢁꢁ4 D8ꢁꢁ4 E8ꢁꢁ3 F8ꢁꢁ3
BRSET4
BSET4
BHCC
LSL
LSLA
LSLX
LSL
LSL
PULX
CLC
EOR
EOR
EOR
EOR
EOR
EOR
3ꢁꢁ
DIR
2ꢁꢁ
DIR
2ꢁꢁrel
2ꢁꢁ
DIR
1ꢁꢁ
INH
1ꢁꢁ
INH
2ꢁꢁIX1 1ꢁꢁIX
1ꢁꢁ
INH
1ꢁꢁ
INH
2ꢁꢁ
IMM
2ꢁꢁ
DIR
3ꢁꢁ
EXT
3ꢁꢁIX2 2ꢁꢁIX1 1ꢁꢁIX
09ꢁꢁ5 19ꢁꢁ5 29ꢁꢁ3 39ꢁꢁ5 49ꢁꢁ1 59ꢁꢁ1 69ꢁꢁ5 79ꢁꢁ4 89ꢁꢁ2 99ꢁꢁ1 A9ꢁꢁ2 B9ꢁꢁ3 C9ꢁꢁ4 D9ꢁꢁ4 E9ꢁꢁ3 F9ꢁꢁ3
BRCLR4
BCLR4
BHCS
ROL
ROLA
ROLX
ROL
ROL
PSHX
SEC
ADC
ADC
ADC
ADC
ADC
ADC
3ꢁꢁ
DIR
2ꢁꢁ
DIR
2ꢁꢁrel
2ꢁꢁ
DIR
1ꢁꢁ
INH
1ꢁꢁ
INH
2ꢁꢁIX1 1ꢁꢁIX
1ꢁꢁ
INH
1ꢁꢁ
INH
2ꢁꢁ
IMM
2ꢁꢁ
DIR
3ꢁꢁ
EXT
3ꢁꢁIX2 2ꢁꢁIX1 1ꢁꢁIX
0Aꢁꢁ5 1Aꢁꢁ5 2Aꢁꢁ3 3Aꢁꢁ5 4Aꢁꢁ1 5Aꢁꢁ1 6Aꢁꢁ5 7Aꢁꢁ4 8Aꢁꢁ3 9Aꢁꢁ1 AAꢁꢁ2 BAꢁꢁ3 CAꢁꢁ4 DAꢁꢁ4 EAꢁꢁ3 FAꢁꢁ3
BRSET5
BSET5
BPL
DEC
DECA
DECX
DEC
DEC
PULH
CLI
ORA
ORA
ORA
ORA
ORA
ORA
3ꢁꢁ
DIR
2ꢁꢁ
DIR
2ꢁꢁrel
2ꢁꢁ
DIR
1ꢁꢁ
INH
1ꢁꢁ
INH
2ꢁꢁIX1 1ꢁꢁIX
1ꢁꢁ
INH
1ꢁꢁ
INH
2ꢁꢁ
IMM
2ꢁꢁ
DIR
3ꢁꢁ
EXT
3ꢁꢁIX2 2ꢁꢁIX1 1ꢁꢁIX
0Bꢁꢁ5 1Bꢁꢁ5 2Bꢁꢁ3 3Bꢁꢁ7 4Bꢁꢁ4 5Bꢁꢁ4 6Bꢁꢁ7 7Bꢁꢁ6 8Bꢁꢁ2 9Bꢁꢁ1 ABꢁꢁ2 BBꢁꢁ3 CBꢁꢁ4 DBꢁꢁ4 EBꢁꢁ3 FBꢁꢁ3
BRCLR5
BCLR5
BMI
DBNZ
DBNZA
DBNZX
DBNZ
DBNZ
PSHH
SEI
ADD
ADD
ADD
ADD
ADD
ADD
3ꢁꢁ
DIR
2ꢁꢁ
DIR
2ꢁꢁrel
3ꢁꢁ
DIR
2ꢁꢁ
INH
2ꢁꢁ
INH
3ꢁꢁIX1 2ꢁꢁIX
1ꢁꢁ
INH
1ꢁꢁ
INH
2ꢁꢁ
IMM
2ꢁꢁ
DIR
3ꢁꢁ
EXT
3ꢁꢁIX2 2ꢁꢁIX1 1ꢁꢁIX
0Cꢁꢁ5 1Cꢁꢁ5 2Cꢁꢁ3 3Cꢁꢁ5 4Cꢁꢁ1 5Cꢁꢁ1 6Cꢁꢁ5 7Cꢁꢁ4 8Cꢁꢁ1 9Cꢁꢁ1
BCꢁꢁ3 CCꢁꢁ4 DCꢁꢁ4 ECꢁꢁ3 FCꢁꢁ3
BRSET6
BSET6
BMC
INC
INCA
INCX
INC
INC
CLRH
RSP
JMP
JMP
JMP
JMP
JMP
3ꢁꢁ
DIR
2ꢁꢁ
DIR
2ꢁꢁrel
2ꢁꢁ
DIR
1ꢁꢁ
INH
1ꢁꢁ
INH
2ꢁꢁIX1 1ꢁꢁIX
1ꢁꢁ
INH
1ꢁꢁ
INH
2ꢁꢁ
DIR
3ꢁꢁ
EXT
3ꢁꢁIX2 2ꢁꢁIX1 1ꢁꢁIX
0Dꢁꢁ5 1Dꢁꢁ5 2Dꢁꢁ3 3Dꢁꢁ4 4Dꢁꢁ1 5Dꢁꢁ1 6Dꢁꢁ4 7Dꢁꢁ3
9Dꢁꢁ1 ADꢁꢁ5 BDꢁꢁ5 CDꢁꢁ6 DDꢁꢁ6 EDꢁꢁ5 FDꢁꢁ5
BRCLR6
BCLR6
BMS
TST
TSTA
TSTX
TST
TST
NOP
BSR
JSR
JSR
JSR
JSR
JSR
3ꢁꢁ
DIR
2ꢁꢁ
DIR
2ꢁꢁrel
2ꢁꢁ
DIR
1ꢁꢁ
INH
1ꢁꢁ
INH
2ꢁꢁIX1 1ꢁꢁIX
1ꢁꢁ
INH
2ꢁꢁrel
2ꢁꢁ
DIR
3ꢁꢁ
EXT
3ꢁꢁIX2 2ꢁꢁIX1 1ꢁꢁIX
0Eꢁꢁ5 1Eꢁꢁ5 2Eꢁꢁ3 3Eꢁꢁ6 4Eꢁꢁ5 5Eꢁꢁ5 6Eꢁꢁ4 7Eꢁꢁ5
8Eꢁ
ꢁ2+
9E
AEꢁꢁ2 BEꢁꢁ3 CEꢁꢁ4 DEꢁꢁ4 EEꢁꢁ3 FEꢁꢁ3
BRSET7
BSET7
BIL
CPHX
3ꢀEXT
MOV
MOV
MOV
MOV
Page
ꢁꢁ2
LDX
LDX
LDX
LDX
LDX
LDX
STOP
3ꢁꢁ
DIR
2ꢁꢁ
DIR
2ꢁꢁrel
3ꢁꢁDD
2ꢁꢀ
DIX+
3ꢁꢁ
IMD
2ꢁꢀ
IX+D
2ꢁꢁ
IMM
2ꢁꢁ
DIR
3ꢁꢁ
EXT
3ꢁꢁIX2 2ꢁꢁIX1 1ꢁꢁIX
1ꢁꢁ
INH
0Fꢁꢁ5 1Fꢁꢁ5 2Fꢁꢁ3 3Fꢁꢁ5 4Fꢁꢁ1 5Fꢁꢁ1 6Fꢁꢁ5 7Fꢁꢁ4
8Fꢁ
ꢁ2+
9Fꢁꢁ1 AFꢁꢁ2 BFꢁꢁ3 CFꢁꢁ4 DFꢁꢁ4 EFꢁꢁ3 FFꢁꢁ2
BRCLR7
BCLR7
BIH
CLR
CLRA
CLRX
CLR
CLR
TXA
AIX
STX
STX
STX
STX
STX
WAIT
3ꢁꢁ
DIR
2ꢁꢁ
DIR
2ꢁꢁrel
2ꢁꢁ
DIR
1ꢁꢁ
INH
1ꢁꢁ
INH
2ꢁꢁIX1 1ꢁꢁIX
1ꢁꢁ
INH
2ꢁꢁ
IMM
2ꢁꢁ
DIR
3ꢁꢁ
EXT
3ꢁꢁIX2 2ꢁꢁIX1 1ꢁꢁIX
1ꢁꢁ
INH
INH
IMM
DIR
EXT
DD
Inherent
rel
relative
SP1
Stack Pointer, 8-Bit Offset
Stack Pointer, 16-Bit offset
Immediate
Direct
IX
Indexed, no offset
Indexed, 8-Bit offset
Indexed, 16-Bit offset
IMM to DIR
SP2
IX+
IX1
Indexed, No offset with post increment
Indexed, 1-Byte offset with post increment
Extended
DIR to DIR
IX+ to DIR
IX2
IX1+
IMD
DIX+
IX+D
DIR to IX+
Opcode in Hexadecimal
ꢁ
F0ꢁ3
HCS08 Cycles
SUB
Instruction Mnemonic
Addressing Mode
Number of Bytes
1ꢁIX
Table 77.ꢀOpcode map (Sheet 2 of 2)
Bit-Manipulation
Branch
Read-Modify-Write
Control
Register/Memory
9E60ꢁ6
9ED0
ꢁꢁ5
9EE0
ꢁꢁ4
NEG
SUB
SUB
3ꢁꢁ
SP1
4ꢁꢁ
SP2
3ꢁꢁ
SP1
FXTH87ERM
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Reference manual
Rev. 5.0 — 4 February 2019
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