NXP Semiconductors
FXTH87E
FXTH87E, Family of Tire Pressure Monitor Sensors
If the associated port pin is not stable for at least two bus clock cycles before changing
to input capture mode, it is possible to get an unexpected indication of an edge trigger.
Typically, a program would clear status flags after changing channel configuration bits
and before enabling channel interrupts or using the status flags to avoid any unexpected
behavior.
11.4.5 Timer channel value registers (TPM1C0VH:TPM1C0VL)
These read/write registers contain the captured TPM1 counter value of the input capture
function or the output compare value for the output compare or PWM functions. The
channel value registers are cleared by reset.
Table 89.ꢀTimer channel 0 value register high (TPM1C0VH) (address $0016)
Bit
R
7
Bit 15
0
6
14
0
5
13
0
4
12
0
3
11
0
2
10
0
1
9
0
0
Bit 8
0
W
Reset
Table 90.ꢀTimer channel 0 value register low (TPM1C0VL) (address $0017)
Bit
R
7
Bit 7
0
6
6
0
5
5
0
4
4
0
3
3
0
2
2
0
1
1
0
0
Bit 0
0
W
Reset
In input capture mode, reading either byte (TPM1C0VH or TPM1C0VL) latches the
contents of both bytes into a buffer where they remain latched until the other byte is read.
This latching mechanism also resets (becomes unlatched) when the TPM1C0SC register
is written.
In output compare or PWM modes, writing to either byte (TPM1C0VH or TPM1C0VL)
latches the value into a buffer. When both bytes have been written, they are transferred
as a coherent 16-bit value into the timer channel value registers. This latching
mechanism may be manually reset by writing to the TPM1C0SC register.
This latching mechanism allows coherent 16-bit writes in either order, which is friendly to
various compiler implementations.
11.4.6 Timer channel 1 status and control register (TPM1C1SC)
TPM1C1SC contains the channel interrupt status flag and control bits that are used to
configure the interrupt enable, channel configuration, and pin function.
Table 91.ꢀTimer channel 1 status and control register (TPM1C1SC) (address $0018)
Bit
R
7
CH1F
0
6
CH1IE
0
5
MS1B
0
4
MS1A
0
3
ELS1B
0
2
ELS1A
0
1
0
0
0
W
Reset
0
0
FXTH87ERM
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Reference manual
Rev. 5.0 — 4 February 2019
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