NXP Semiconductors
FXTH87E
FXTH87E, Family of Tire Pressure Monitor Sensors
Bit-Manipulation
Branch
Read-Modify-Write
9E61ꢁ6
Control
Register/Memory
9ED1ꢁ5 9EE1ꢁ4
CBEQ
CMP
CMP
4ꢁSP1
4ꢁSP2
3ꢁSP1
9ED2ꢁ5 9EE2ꢁ4
SBC
SBC
4ꢁSP2
3ꢁSP1
9E63ꢁ6
COM
9ED3ꢁ5 9EE3ꢁ4 9EF3ꢁ6
CPX
CPX
CPHX
3ꢁSP1
4ꢁSP2
3ꢁSP1
3ꢁSP1
9E64ꢁ6
LSR
9ED4ꢁ5 9EE4ꢁ4
AND
AND
3ꢁSP1
4ꢁSP2
3ꢁSP1
9ED5ꢁ5 9EE5ꢁ4
BIT
BIT
4ꢁSP2
3ꢁSP1
9E66ꢁ6
ROR
9ED6ꢁ5 9EE6ꢁ4
LDA
LDA
3ꢁSP1
4ꢁSP2
3ꢁSP1
9E67ꢁ6
ASR
9ED7ꢁ5 9EE7ꢁ4
STA
STA
3ꢁSP1
4ꢁSP2
3ꢁSP1
9E68ꢁ6
LSL
9ED8ꢁ5 9EE8ꢁ4
EOR
EOR
3ꢁSP1
4ꢁSP2
3ꢁSP1
9E69ꢁ6
ROL
9ED9ꢁ5 9EE9ꢁ4
ADC
ADC
3ꢁSP1
4ꢁSP2
3ꢁSP1
9E6Aꢁ6
DEC
9EDAꢁ5 9EEAꢁ4
ORA
ORA
3ꢁSP1
4ꢁSP2
3ꢁSP1
9E6Bꢁ8
DBNZ
9EDBꢁ5 9EEBꢁ4
ADD
ADD
4ꢁSP1
4ꢁSP2
3ꢁSP1
9E6Cꢁ6
INC
3ꢁSP1
9E6Dꢁ5
TST
3ꢁSP1
9EAEꢁ5 9EBEꢁ6 9ECEꢁ5 9EDEꢁ5 9EEEꢁ4 9EFEꢁ5
LDHX
2ꢁIX
LDHX
LDHX
LDX
LDX
LDHX
4ꢁIX2
3ꢁIX1
4ꢁSP2
3ꢁSP1
3ꢁSP1
9E6Fꢁ6
CLR
9EDFꢁ5 9EEFꢁ4 9EFFꢁ5
STX
STX
STHX
3ꢁSP1
4ꢁSP2
3ꢁSP1
3ꢁSP1
INH
Inherent
REL
IX
relative
SP1
SP2
IX+
Stack Pointer, 8-Bit Offset
Stack Pointer, 16-Bit offset
IMM
DIR
EXT
DD
Immediate
Direct
Indexed, no offset
Indexed, 8-Bit offset
Indexed, 16-Bit offset
IMM to DIR
IX1
Indexed, No offset with post increment
Indexed, 1-Byte offset with post increment
Extended
DIR to DIR
IX+ to DIR
IX2
IX1+
IMD
DIX+
IX+D
DIR to IX+
Note: All Sheet 2 Opcodes are Preceded by the Page 2 Prebyte (9E)
Prebyte (9E) and Opcode in Hexadecimal
9E60ꢁ6
HCS08 Cycles
ꢁ
SUB
Instruction Mnemonic
Addressing Mode
Number of Bytes
3ꢁSP1
11 Timer Pulse-Width Module
The timer pulse-width module (TPM1) is a two channel timer system that supports
traditional input capture, output compare, or edge-aligned PWM on each channel. All
FXTH87ERM
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Reference manual
Rev. 5.0 — 4 February 2019
84 / 183
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