NXP Semiconductors
FXTH87E
FXTH87E, Family of Tire Pressure Monitor Sensors
to ensure operation within specified limits. After these trim values are written, they remain
constant until the next MCU reset.
The application program must set up control bits and registers to configure the LFR to
determine the structure of the message telegram, the input sensitivity, and other LFR
options. It is good practice to clear the flags in the LFS register before enabling interrupt
sources in order to avoid any immediate interrupt requests.
14.17 LFR register definition
The LFR module uses eight addresses in the MCU memory map for data, control, and
status registers. This section consists of register descriptions. Each control register
(LFCTLx) should be modify when the LF is off (LFEN = 0). Modification of the control
registers "on-the-fly" might lead to unknown state. Each turn off of the LFR (LFEN
= 0) should be followed by at least two LFO cycles before trying to restart the LFR
(LFEN = 1).
14.17.1 LF control register 1 (LFCTL1)
LFCTL1 contains the main LF enable control, detection protocol format controls, and
input sensitivity controls. The LFCTL1 register also contains a register select bit, LPAGE.
Table 106.ꢀLFR control register 1 (LFCTL1) (address $0020)
Bit
R
7
LFEN
0
6
5
CARMOD
0
4
LPAGE
0
3
2
1
0
0
SRES
0
IDSEL[1:0]
SENS[1:0]
W
Reset
0
0
0
0
Table 107.ꢀLFCTL1 register field descriptions
Field
Description
LF Enable — This read-write control bit is used to enable or disable the LF receiver. Once this bit is set
the LFR will go through a power-up sequence that starts on the next rising edge of the LFO clock. The first
complete cycle of the LFO is used to power up the LFR circuits. Following this startup time the auto-zero
sequence is performed for 64 μsec and then the LFR is ready to receive signals.
7
LFEN
0ꢀLF receiver in standby
1ꢀLF receiver active
Soft Reset — This read/write bit controls the soft reset of the LFR. The bit is self reset and always reads as
a logical zero.
6
0ꢀReset completed
1ꢀStart a soft reset
SRES
Carrier Mode — This read/write control bit selects the basic operating mode for the LFR.
0ꢀData receive mode
5
CARMOD
1ꢀCarrier detect mode — wake the MCU when a carrier signal is detected if LFCDIE is set
LFR Page Select — This read/write bit is used is used to select the register page access. The LPAGE bit
has no effect on the LFCTL1 and LFCTL2 registers. This bit is cleared by LFR reset.
4
0ꢀAccess page 0
1ꢀAccess page 1
LPAGE
FXTH87ERM
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2019. All rights reserved.
Reference manual
Rev. 5.0 — 4 February 2019
122 / 183
NXP [ NXP ]
