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NANO102ZD1AN 参数 Datasheet PDF下载

NANO102ZD1AN图片预览
型号: NANO102ZD1AN
PDF下载: 下载PDF文件 查看货源
内容描述: [ARM® Cortex®-M 32-bit Microcontroller]
分类和应用: 微控制器
文件页数/大小: 95 页 / 2021 K
品牌: NUVOTON [ NUVOTON ]
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Nano100(A)  
1/16, 1/8, 1/4, 1/2 and 1 second  
Wake system up from Power-down or Idle mode  
Support 80 bytes spare registers and a snoop pin to clear the content of these  
spare registers  
PWM/Capture  
Support 2 PWM module, each has two 16-bit PWM generators  
Provide eight PWM outputs or four complementary paired PWM outputs  
Each PWM generator equipped with one clock divider, one 8-bit prescaler , two  
clock selectors, and one Dead-Zone generator for complementary paired PWM  
Up to eight 16-bit digital Capture timers (shared with PWM timers) provide eight  
rising/falling capture inputs  
Support one shot and continuous mode  
Support Capture interrupt  
UART  
Up to two 16-byte FIFO UART controllers  
SPI  
UART ports with flow control (TX, RX, CTSn and RTSn)  
Supports IrDA (SIR) function  
Supports LIN function  
Supports RS-485 9 bit mode and direction control. (Low Density Only)  
Programmable baud rate generator  
Supports PDMA mode  
Wake system up from Power-down or Idle mode  
Up to three sets of SPI controller  
Master up to 16 MHz, and Slave up to 6 MHz  
Supports SPI/MICROWIRE Master/Slave mode  
Full duplex synchronous serial data transfer  
Variable length of transfer data from 4 to 32 bits  
MSB or LSB first data transfer  
RX and TX on both rising or falling edge of serial clock independently  
Two slave/device select lines when SPI controller is as the master, and 1  
slave/device select line when SPI controller is as the slave  
Supports byte suspend mode in 32-bit transmission  
Supports two channel PDMA requests, one for transmit and another for receive  
Supports three wire, no slave select signal, bi-direction interface  
Wake system up from Power-down or Idle mode  
I2C  
Up to two sets of I2C device  
Mar 31, 2015  
Page 16 of 95  
Revision V1.00  
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